formulasearchengine - User contributions [en]

Annapolis Valley

2014-01-31T20:33:33Z

142.177.9.209:

The stylish wardrobe of Maggie Gyllenhaal�s role in BBC Two�s hard-hitting political thriller, The Honourable Woman, has caught the attention of the eagle-eyed viewers. The eight-part series, set against the backdrop of the Israeli-Palestinian conflict, centres around Nessa Stein, played by Gyllenhaal. Stein is an Anglo-Israeli businesswoman recently ennobled in the House of Lords who devotes herself to philanthropic purposes across the Middle East, but hides a secret past from her time spent in Gaza eight years earlier. Through the unravelling of her public and private life played out on an international, political stage, Stein parades in an increasingly impressive selection of outfits. �Because the character of Nessa is so complicated and multi layered, we looked at all sorts of different people as reference. I suppose we started off by looking at other powerful and stylish women through history, Jackie Kennedy, Eva Peron, Margaret Thatcher, Cleopatra� Edward K Gibbon costume designer for the series told The Independent 
Maggie Gyllenhaal The Honourable Woma 
�And then we kind of threw all the reference away and started afresh. The way Maggie looked as Nessa was constantly evolving throughout the six month shoot.�
The series opens with Nessa clad in a Roland [http://Photobucket.com/images/Mouret+power Mouret power] dress. Her day to day look is a sartorial dream with tailored suits by the likes of Stella McCartney, Acne, Escada, Pringle and vintage Chane 
�Silk blouses and wide legged pants based on 1970s Yves Saint Laurent originals were created by Hilary Marschner� explains Gibb 

Outerwear includes coats by Mulberry, vintage finds from Jil Sander and a 1980s Gieves and Hawkes men�s co .
Even curled up in her panic room at night she sports silk slips by haute couture Parisian lingerie designer Carine Gilson and London based lingerie label Bod .
In pictures: Nessa Stein's wardrobe in The Honourable Woma 
Shoes are by Acne, Christian Louboutin and [http://www.pcs-systems.co.uk/Images/celinebag.aspx Cheap Celine Bags]. With bags from Mulberry and John Lewis. �Nessa's wardrobe runs the full gamut from designer, through High Street, Charity shops and bespoke pieces� says Gib 

�The clothing is always the way in [to the character]� Gyllenhaal told WWD. �I never played a character that didn�t care about what they were wearing.�
The Honourable Woman continues tonight, BBC2 at 9pm.

Dispersion (water waves)

2014-01-22T13:52:20Z

142.177.138.94: /* Surface tension effects */

{{Redirect|Sigma delta|the sorority|Sigma Delta}}
{{Multiple issues|cleanup = June 2011|technical = June 2011|refimprove = December 2011}}

'''Delta-sigma''' ('''ΔΣ'''; or '''sigma-delta''', '''ΣΔ''') modulation is a method for encoding [[analog signal]]s into [[digital signal]]s or higher-resolution digital signals into lower-resolution digital signals.

The conversion is done using error feedback, where the difference between the two signals is measured and used to improve the conversion. The low-resolution signal typically changes more quickly than the high-resolution signal and it can be filtered to recover the high-resolution signal with little or no loss of fidelity. This technique has found increasing use in modern electronic components such as [[Analog-to-digital converter|converters]], [[frequency synthesizer]]s, [[Switched-mode power supply|switched-mode power supplies]] and [[motor controller]]s.

Both [[analog-to-digital converter]]s (ADCs) and [[digital-to-analog converter]]s (DACs) can employ delta-sigma modulation. A delta-sigma ADC first encodes an analog signal using delta-sigma modulation and then applies a digital filter to form a higher-resolution digital output. On the other hand, a delta-sigma DAC encodes a high-resolution digital input signal into a lower-resolution signal that is mapped to [[voltage]]s and then smoothed with an analog filter. In both cases, the temporary use of a lower-resolution signal simplifies circuit design and improves efficiency.

The coarsely-quantized output of a delta-sigma modulator is occasionally used directly in signal processing or as a representation for signal storage. For example, the [[Super Audio CD]] (SACD) stores the output of a delta-sigma modulator directly on a disk.

== Motivation ==

===Why convert an analog signal into a stream of pulses?===
In brief, because it is very easy to regenerate pulses at the receiver into the ideal form transmitted. The only part of the transmitted waveform required at the receiver is the time at which the pulse occurred. Given the timing information the transmitted waveform can be reconstructed electronically with great precision. In contrast, without conversion to a pulse stream but simply transmitting the analog signal directly, all [[Noise (electronics)|noise]] in the system is added to the analog signal, reducing its quality.

Each pulse is made up of a step up followed after a short interval by a step down. It is possible, even in the presence of electronic noise, to recover the timing of these steps and from that regenerate the transmitted pulse stream almost noiselessly. Then the accuracy of the transmission process reduces to the accuracy with which the transmitted pulse stream represents the input waveform.

===Why delta-sigma modulation?===
Delta-sigma modulation converts the analog voltage into a pulse frequency and is alternatively known as Pulse Density modulation or Pulse Frequency modulation. In general, frequency may vary smoothly in infinitesimal steps, as may voltage, and both may serve as an analog of an infinitesimally varying physical variable such as acoustic pressure, light intensity, etc. The substitution of frequency for voltage is thus entirely natural and carries in its train the transmission advantages of a pulse stream. The different names for the modulation method are the result of pulse frequency modulation by different electronic implementations, which all produce similar transmitted waveforms.

===Why the delta-sigma analog to digital conversion?===
The ADC converts the mean of an analog voltage into the mean of an analog pulse frequency and counts the pulses in a known interval so that the pulse count divided by the interval gives an accurate digital representation of the mean analog voltage during the interval. This interval can be chosen to give any desired resolution or accuracy. The method is cheaply produced by modern methods; and it is widely used.

==Analog to digital conversion==

=== Description ===
The ADC generates a pulse stream in which the frequency of pulses in the stream is proportional to the analog voltage input, <math>v</math>, so that the frequency, <math>f = k \cdot v</math> where k is a constant for the particular implementation.

A counter sums the number of pulses that occur in a predetermined period, <math>P</math> so that the sum, <math>\Sigma</math>, is <math>P \cdot f = k \cdot P \cdot v</math>.

<math>k \cdot P</math> is chosen so that a digital display of the count, <math>\Sigma</math>, is a display of <math>v</math> with a predetermined scaling factor. Because <math>P</math> may take any designed value it may be made large enough to give any desired resolution or accuracy.

Each pulse of the pulse stream has a known, constant [[amplitude]] <math>V</math> and duration <math>\operatorname{d}t</math>, and thus has a known [[integral]] <math>V\operatorname{d}t</math> but variable separating interval.

In a formal analysis an impulse such as integral <math>V\operatorname{d}t</math> is treated as the [[Dirac delta function|Dirac δ (delta) function]] and is specified by the step produced on integration. Here we indicate that step as <math>\Delta = \int V\operatorname{d}t</math>.

The interval between pulses, ''p'', is determined by a feedback loop arranged so that <math>p = \frac{1}{f} = \frac{1}{k \cdot v}</math>.

The action of the feedback loop is to monitor the integral of v and when that integral has incremented by <math>\Delta</math>, which is indicated by the integral waveform crossing a threshold, then subtracting <math>\Delta</math> from the integral of v so that the combined waveform sawtooths between the threshold and ( threshold - <math>\Delta</math> ). At each step a pulse is added to the pulse stream.

Between impulses the slope of the integral is proportional to <math>v = A \cdot v = \frac{\Delta}{p} = \Delta \cdot f = \Delta \cdot k \cdot v</math>. Whence <math>A = \Delta \cdot k</math>.

It is the pulse stream which is transmitted for delta-sigma modulation but the pulses are counted to form sigma in the case of analogue to digital conversion.

=== Analysis ===
[[Image:Block Diagram Delta-Sigma.svg|DeltaSigma1.svg|thumb|500px|Fig. 1: Block diagram and waveforms for a sigma delta ADC.]]
[[Image:Fig 1a.svg|Fig_1a.svg|thumb|500px|Fig. 1a: Effect of clocking impulses]]
Shown below the block diagram illustrated in Fig. 1 are waveforms at points designated by numbers 1 to 5 for an input of 0.2 volts on the left and 0.4 volts on the right.

In most practical applications the summing interval is large compared with the impulse duration and for signals which are a significant fraction of full scale the variable separating interval is also small compared with the summing interval. The [[Nyquist–Shannon sampling theorem]] requires two samples to render a varying input signal. The samples appropriate to this criterion are two successive Σ counts taken in two successive summing intervals. The summing interval, which must accommodate a large count in order to achieve adequate precision, is inevitably long so that the converter can only render relatively low frequencies. Hence it is convenient and fair to represent the input voltage (1) as constant over a few impulses.

Consider first the waveforms on the left.

1 is the input and for this short interval is constant at 0.2 V. The stream of delta impulses is shown at 2 and the difference between 1 and 2 is shown at 3. This difference is integrated to produce the waveform 4. The threshold detector generates a pulse 5 which starts as the waveform 4 crosses the threshold and is sustained until the waveform 4 falls below the threshold. Within the loop 5 triggers the impulse generator and external to the loop increments the counter. The summing interval is a prefixed time and at its expiry the count is strobed into the buffer and the counter reset.

It is necessary that the ratio between the impulse interval and the summing interval is equal to the maximum (full scale) count. It is then possible for the impulse duration and the summing interval to be defined by the same clock with a suitable arrangement of logic and counters. This has the advantage that neither interval has to be defined with absolute precision as only the ratio is important. Then to achieve overall accuracy it is only necessary that the amplitude of the impulse be accurately defined.

On the right the input is now 0.4 V and the sum during the impulse is −0.6 V as opposed to −0.8 V on the left. Thus the negative slope during the impulse is lower on the right than on the left.

Also the sum is 0.4 V on the right during the interval as opposed to 0.2 V on the left. Thus the positive slope outside the impulse is higher on the right than on the left.

The resultant effect is that the integral (4) crosses the threshold more quickly on the right than on the left. A full analysis would show that in fact the interval between threshold crossings on the right is half that on the left. Thus the frequency of impulses is doubled. Hence the count increments at twice the speed on the right to that on the left which is consistent with the input voltage being doubled.

Construction of the waveforms illustrated at (4) is aided by concepts associated with the Dirac delta function in that all impulses of the same strength produce the same step when integrated, by definition. Then (4) is constructed using an intermediate step (6) in which each integrated impulse is represented by a step of the assigned strength which decays to zero at the rate determined by the input voltage. The effect of the finite duration of the impulse is constructed in (4) by drawing a line from the base of the impulse step at zero volts to intersect the decay line from (6) at the full duration of the impulse.

As stated, Fig. 1 is a simplified block diagram of the delta-sigma ADC in which the various functional elements have been separated out for individual treatment and which tries to be independent of any particular implementation. Many particular implementations seek to define the impulse duration and the summing interval from the same clock as discussed above but in such a way that the start of the impulse is delayed until the next occurrence of the appropriate clock pulse boundary. The effect of this delay is illustrated in Fig. 1a for a sequence of impulses which occur at a nominal 2.5 clock intervals, firstly for impulses generated immediately the threshold is crossed as previously discussed and secondly for impulses delayed by the clock. The effect of the delay is firstly that the ramp continues until the onset of the impulse, secondly that the impulse produces a fixed amplitude step so that the integral retains the excess it acquired during the impulse delay and so the ramp restarts from a higher point and is now on the same locus as the unclocked integral. The effect is that, for this example, the undelayed impulses will occur at clock points 0, 2.5, 5, 7.5, 10, etc. and the clocked impulses will occur at 0, 3, 5, 8, 10, etc. The maximum error that can occur due to clocking is marginally less than one count. Although the Sigma-Delta converter is generally implemented using a common clock to define the impulse duration and the summing interval it is not absolutely necessary and an implementation in which the durations are independently defined avoids one source of noise, the noise generated by waiting for the next common clock boundary. Where noise is a primary consideration that overrides the need for absolute amplitude accuracy; e.g., in bandwidth limited signal transmission, separately defined intervals may be implemented.

=== Practical Implementation ===
[[Image:Fig. 1b.svg|Fig. 1b.svg|thumb|500px|Fig. 1b: circuit diagram]]
[[Image:Fig 1c.svg|Fig_1c.svg|thumb|500px|Fig. 1c: ADC waveforms]]
A circuit diagram for a practical implementation is illustrated, Fig 1b and the associated waveforms Fig. 1c. This circuit diagram is mainly for illustration purposes, details of particular manufacturers implementations will usually be available from the particular manufacturer. A scrap view of an alternative front end is shown in Fig. 1b which has the advantage that the voltage at the switch terminals are relatively constant and close to 0.0 V. Also the current generated through R by −Vref is constant at −Vref/R so that much less noise is radiated to adjacent parts of the circuit. Then this would be the preferred front end in practice but, in order to show the impulse as a voltage pulse so as to be consistent with previous discussion, the front end given here, which is an electrical equivalent, is used.

From the top of Fig 1c the waveforms, labelled as they are on the circuit diagram, are:-

The clock.

(a) Vin. This is shown as varying from 0.4 V initially to 1.0 V and then to zero volts to show the effect on the feedback loop.

(b) The impulse waveform. It will be discovered how this acquires its form as we traverse the feedback loop.

(c) The current into the capacitor, Ic, is the linear sum of the impulse voltage upon R and Vin upon R. To show this sum as a voltage the product R × Ic is plotted. The input impedance of the amplifier is regarded as so high that the current drawn by the input is neglected.

(d) The negated integral of Ic. This negation is standard for the op. amp. implementation of an integrator and comes about because the current into the capacitor at the amplifier input is the current out of the capacitor at the amplifier output and the voltage is the integral of the current divided by the capacitance of C.

(e) The comparator output. The comparator is a very high gain amplifier with its plus input terminal connected for reference to 0.0 V. Whenever the negative input terminal is taken negative with respect the positive terminal of the amplifier the output saturates positive and conversely negative saturation for positive input. Thus the output saturates positive whenever the integral (d) goes below the 0 V reference level and remains there until (d) goes positive with respect to the reference level.

(f) The impulse timer is a D type positive edge triggered flip flop. Input information applied at D is transferred to Q on the occurrence of the positive edge of the clock pulse. thus when the comparator output (e) is positive Q goes positive or remains positive at the next positive clock edge. Similarly, when (e) is negative Q goes negative at the next positive clock edge. Q controls the electronic switch to generate the current impulse into the integrator. Examination of the waveform (e) during the initial period illustrated, when Vin is 0.4 V, shows (e) crossing the threshold well before the trigger edge (positive edge of the clock pulse) so that there is an appreciable delay before the impulse starts. After the start of the impulse there is further delay while (e) climbs back past the threshold. During this time the comparator output remains high but goes low before the next trigger edge. At that next trigger edge the impulse timer goes low to follow the comparator. Thus the clock determines the duration of the impulse. For the next impulse the threshold is crossed immediately before the trigger edge and so the comparator is only briefly positive. Vin (a) goes to full scale, +Vref, shortly before the end of the next impulse. For the remainder of that impulse the capacitor current (c) goes to zero and hence the integrator slope briefly goes to zero. Following this impulse the full scale positive current is flowing (c) and the integrator sinks at its maximum rate and so crosses the threshold well before the next trigger edge. At that edge the impulse starts and the Vin current is now matched by the reference current so that the net capacitor current (c) is zero. Then the integration now has zero slope and remains at the negative value it had at the start of the impulse. This has the effect that the impulse current remains switched on because Q is stuck positive because the comparator is stuck positive at every trigger edge. This is consistent with contiguous, butting impulses which is required at full scale input.

Eventually Vin (a) goes to zero which means that the current sum (c) goes fully negative and the integral ramps up. It shortly thereafter crosses the threshold and this in turn is followed by Q, thus switching the impulse current off. The capacitor current (c) is now zero and so the integral slope is zero, remaining constant at the value it had acquired at the end of the impulse.

(g) The countstream is generated by gating the negated clock with Q to produce this waveform. Thereafter the summing interval, sigma count and buffered count are produced using appropriate counters and registers. The Vin waveform is approximated by passing the countstream (g) into a low pass filter, however it suffers from the defect discussed in the context of Fig. 1a. One possibility for reducing this error is to halve the feedback pulse length to half a clock period and double its amplitude by halving the impulse defining resistor thus producing an impulse of the same strength but one which never butts onto its adjacent impulses. Then there will be a threshold crossing for every impulse. In this arrangement a monostable flip flop triggered by the comparator at the threshold crossing will closely follow the threshold crossings and thus eliminate one source of error, both in the ADC and the sigma delta modulator.

=== Remarks ===

In this section we have mainly dealt with the analogue to digital converter as a stand alone function which achieves astonishing accuracy with what is now a very simple and cheap architecture. Initially the Delta-Sigma configuration was devised by INOSE et al. to solve problems in the accurate transmission of analog signals. In that application it was the pulse stream that was transmitted and the original analog signal recovered with a low pass filter after the received pulses had been reformed. This low pass filter performed the summation function associated with Σ. The highly mathematical treatment of transmission errors was introduced by them and is appropriate when applied to the pulse stream but these errors are lost in the accumulation process associated with Σ to be replaced with the errors associated with the mean of means when discussing the ADC. For those uncomfortable with this assertion consider this.

It is well known that by Fourier analysis techniques the incoming waveform can be represented over the summing interval by the sum of a constant plus a fundamental and harmonics each of which has an exact integer number of cycles over the sampling period. It is also well known that the integral of a sine wave or cosine wave over one or more full cycles is zero. Then the integral of the incoming waveform over the summing interval reduces to the integral of the constant and when that integral is divided by the summing interval it becomes the mean over that interval. The interval between pulses is proportional to the inverse of the mean of the input voltage during that interval and thus over that interval, ts, is a sample of the mean of the input voltage proportional to V/ts. Thus the average of the input voltage over the summing period is VΣ/N and is the mean of means and so subject to little variance.

Unfortunately the analysis for the transmitted pulse stream has, in many cases, been carried over, uncritically, to the ADC.

It was indicated in section 2.2 Analysis that the effect of constraining a pulse to only occur on clock boundaries is to introduce noise, that generated by waiting for the next clock boundary. This will have its most deleterious effect on the high frequency components of a complex signal. Whilst the case has been made for clocking in the ADC environment, where it removes one source of error, namely the ratio between the impulse duration and the summing interval, it is deeply unclear what useful purpose clocking serves in a single channel transmission environment since it is a source of both noise and complexity but it is conceivable that it would be useful in a TDM ([[time division multiplex]]) environment.

A very accurate transmission system with constant sampling rate may be formed using the full arrangement shown here by transmitting the samples from the buffer protected with redundancy error correction. In this case there will be a trade off between bandwidth and N, the size of the buffer. The signal recovery system will require redundancy error checking, digital to analog conversion,and sample and hold circuitry. A possible further enhancement is to include some form of slope regeneration.This amounts to PCM (pulse code modulation) with digitization performed by a sigma-delta ADC.

The above description shows why the impulse is called delta. The integral of an impulse is a step. A one bit DAC may be expected to produce a step and so must be a conflation of an impulse and an integration. The analysis which treats the impulse as the output of a 1-bit DAC hides the structure behind the name (sigma delta) and cause confusion and difficulty interpreting the name as an indication of function. This analysis is very widespread but is deprecated.

A modern alternative method for generating voltage to frequency conversion is discussed in synchronous voltage to frequency converter (SVFC) which may be followed by a counter to produce a digital representation in a similar manner to that described above.<ref>
[http://www.analog.com/static/imported-files/tutorials/MT-028.pdf Voltage-to-Frequency Converters] by Walt Kester and James Bryant 2009. Analog Devices.
</ref>

==Digital to analog conversion==

=== Discussion ===
Delta-sigma modulators are often used in [[digital to analog converter]]s (DACs). In general, a DAC converts a digital number representing some analog value into that analog value. For example, the analog voltage level into a speaker may be represented as a 20 bit digital number, and the DAC converts that number into the desired voltage. To actually drive a load (like a speaker) a DAC is usually connected to or integrated with an [[electronic amplifier]].

This can be done using a delta-sigma modulator in a [[Class D Amplifier]]. In this case, a multi-bit digital number is input to the delta-sigma modulator, which converts it into a faster sequence of 0's and 1's. These 0's and 1's are then converted into analog voltages. The conversion, usually with MOSFET drivers, is very efficient in terms of power because the drivers are usually either fully on or fully off, and in these states have low power loss.

The resulting two-level signal is now like the desired signal, but with higher frequency components to change the signal so that it only has two levels. These added frequency components arise from the [[quantization error]] of the delta-sigma modulator, but can be filtered away by a simple [[low-pass filter]]. The result is a reproduction of the original, desired analog signal from the digital values.

The circuit itself is relatively inexpensive. The digital circuit is small, and the MOSFETs used for the power amplification are simple. This is in contrast to a multi-bit DAC which can have very stringent design conditions to precisely represent digital values with a large number of bits.

The use of a delta-sigma modulator in the digital to analog conversion has enabled a cost-effective, low power, and high performance solution.

== Relationship to Δ-modulation ==
[[Image:FromDtoDS raster.png|thumb|500px|right|Fig. 2: Derivation of ΔΣ- from Δ-modulation]]
ΔΣ modulation (SDM) is inspired by [[delta modulation|Δ modulation]] (DM), as shown in Fig. 2. If [[Quantization (signal processing)|quantization]] were [[Homogeneous function|homogeneous]] (e.g., if it were [[linear]]), the following would be a sufficient derivation of the equivalence of DM and SDM:
# Start with a block diagram of a Δ-modulator/demodulator.
# The linearity property of integration (<math>\scriptstyle \int a \,+\, \int b \,=\, \int (a \,+\, b)</math>) makes it possible to move the integrator, which reconstructs the analog signal in the demodulator section, in front of the Δ-modulator.
# Again, the linearity property of the integration allows the two integrators to be combined and a ΔΣ-modulator/demodulator block diagram is obtained.
However, the quantizer is '''not''' homogeneous, and so this explanation is flawed. It's true that ΔΣ is ''inspired'' by Δ-modulation, but the two are distinct in operation. From the first block diagram in Fig. 2, the integrator in the feedback path can be removed if the feedback is taken directly from the input of the low-pass filter. Hence, for delta modulation of input signal <math>\scriptstyle u</math>, the low-pass filter sees the signal
:<math>y_\text{DM} = \int \operatorname{Quantize}\left( u - y_\text{DM} \right).\,</math>
However, sigma-delta modulation of the same input signal places at the low-pass filter
:<math>y_\text{SDM} = \operatorname{Quantize}\left( \int \left( u - y_\text{SDM} \right)\right).\,</math>
In other words, SDM and DM swap the position of the integrator and quantizer. The net effect is a simpler implementation that has the added benefit of [[noise shaping|shaping]] the quantization noise away from signals of interest (i.e., signals of interest are low-pass filtered while quantization noise is high-pass filtered). This effect becomes more dramatic with increased [[oversampling]], which allows for quantization noise to be somewhat programmable. On the other hand, Δ-modulation shapes both noise and signal equally.

Additionally, the quantizer (e.g., [[comparator]]) used in DM has a small output representing a small step up and down the quantized approximation of the input while the quantizer used in SDM must take values ''outside'' of the range of the input signal, as shown in Fig. 3.
[[Image:Pulse-density modulation 1 period.gif|thumb|center|499px|Fig. 3: An example of SDM of 100 samples of one period a sine wave. 1-bit samples (e.g., comparator output) overlaid with sine wave where logic high (e.g., <math>\scriptstyle +V_{CC}</math>) represented by blue and logic low (e.g., <math>\scriptstyle -V_{CC}</math>) represented by white.]]

In general, ΔΣ has some advantages versus Δ modulation:
* The whole structure is simpler:
** Only one integrator is needed
** The demodulator can be a simple linear filter (e.g., RC or LC filter) to reconstruct the signal
** The quantizer (e.g., comparator) can have full-scale outputs
* The quantized value is the integral of the difference signal, which makes it less sensitive to the rate of change of the signal.

== Principle ==
The principle of the ΔΣ architecture is explained at length in section 2. Initially, when a sequence starts, the circuit will have an arbitrary state which is dependant on the integral of all previous history. In mathematical terms this corresponds to the arbitrary integration constant of the indefinite integral. This follows from the fact that at the heart of the method there is an integrator which can have any arbitrary state dependant on previous input, see Fig. 1c (d). From the occurrence of the first pulse onward the frequency of the pulse stream is proportional to the input voltage to be transformed. A demonstration applet is available online to simulate the whole architecture.<ref>[http://designtools.analog.com/dt/sdtutorial/sdtutorial.html Analog Devices : Virtual Design Center : Interactive Design Tools : Sigma-Delta ADC Tutorial]</ref>

== Variations ==

There are many kinds of ADC that use this delta-sigma structure.
The above analysis focuses on the simplest 1st-order, 2-level, uniform-decimation sigma-delta ADC.
Many ADCs use a second-order 5-level sinc3 sigma-delta structure.

=== 2nd order and higher order modulator ===
[[Image:DeltaSigma2.svg|thumb|500px|Fig. 4: Block diagram of a 2nd order ΔΣ modulator]]
The number of integrators, and consequently, the numbers of feedback loops, indicates the ''order'' of a ΔΣ-modulator; a 2nd order ΔΣ modulator is shown in Fig. 4. First order modulators are unconditionally stable, but stability analysis must be performed for higher order modulators.

=== 3-level and higher quantizer ===
The modulator can also be classified by the number of bits it has in output, which strictly depends on the output of the quantizer. The quantizer can be realized with a ''N-level'' comparator, thus the modulator has ''log2N''-bit output.
A simple comparator has 2 levels and so is 1 bit quantizer; a 3-level quantizer is called a "1.5" bit quantizer; a 4-level quantizer is a 2 bit quantizer; a 5-level quantizer is called a "2.5 bit" quantizer.<ref>
[http://www.faqs.org/patents/app/20090072897 Sigma-delta class-D amplifier and control method for a sigma-delta class-D amplifier] by Jwin-Yen Guo and Teng-Hung Chang
</ref>

=== Decimation structures ===
The conceptually simplest decimation structure is a counter that is reset to zero at the beginning of each integration period, then read out at the end of the integration period.

The multi-stage noise shaping (MASH) structure has a noise shaping property, and is commonly used in digital audio and fractional-N frequency synthesizers. It comprises two or more cascaded overflowing accumulators, each of which is equivalent to a first-order sigma delta modulator. The carry outputs are combined through summations and delays to produce a binary output, the width of which depends on the number of stages (order) of the MASH. Besides its noise shaping function, it has two more attractive properties:
* simple to implement in hardware; only common digital blocks such as [[Accumulator (computing)|accumulators]], [[Adder (electronics)|adders]], and [[D flip-flop]]s are required
* unconditionally stable (there are no feedback loops outside the accumulators)

A very popular decimation structure is the ''sinc'' filter. For 2nd order modulators, the ''sinc3'' filter is close to optimum.<ref>
[http://www.slac.stanford.edu/econf/C0604032/papers/0232.PDF A Novel Architecture for DAQ in Multi-channel, Large Volume, Long Drift Liquid Argon TPC]
by S. Centro, G. Meng, F. Pietropaola, S. Ventura 2006
</ref><ref>
[http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4253561 A Low Power Sinc3 Filter for ΣΔ Modulators]
by A. Lombardi, E. Bonizzoni, P. Malcovati, F. Maloberti 2007
</ref>

== Quantization theory formulas ==
{{Main|Quantization (signal processing)}}
When a signal is quantized, the resulting signal approximately has the second-order statistics of a signal with independent additive white noise. Assuming that the signal value is in the range of one step of the quantized value with an equal distribution, the root mean square value of this quantization noise is

:<math>e_\mathrm{rms}\, =\sqrt{\, \frac{1}{\Delta}\int_{-\Delta/2}^{+\Delta/2} e^2\, de\, }=\, \frac{\Delta}{2\sqrt{3}}</math>

In reality, the quantization noise is of course not independent of the signal; this dependence is the source of idle tones and pattern noise in Sigma-Delta converters.

Over sampling ratio (OSR), where <math>f_\mathrm{s}</math> is the sampling frequency and <math>2f_0</math> is [[Nyquist rate]]

:<math>\mathrm{OSR}\,=\,\frac{f_s}{2f_0}\,=\,\frac{1}{2f_0\tau}</math>

The [[Root mean square|RMS]] noise voltage within the band of interest can be expressed in terms of OSR

:<math>\mathrm{n_0}\,=\, \frac{e_{rms}}{\sqrt{OSR}}</math>

== Oversampling ==
[[Image:DeltaSigmaNoise.svg|thumb|320px|right|Fig. 5: Noise shaping curves and noise spectrum in ΔΣ modulator]]
{{Main|Oversampling}}
Let's consider a signal at frequency <math>\scriptstyle f_0</math> and a sampling frequency of <math>\scriptstyle f_\mathrm{s}</math> much higher than Nyquist rate (see fig. 5). ΔΣ modulation is based on the technique of oversampling to reduce the noise in the band of interest (green), which also avoids the use of high-precision analog circuits for the ''[[anti-aliasing filter]]''. The quantization noise is the same both in a Nyquist converter (in yellow) and in an oversampling converter (in blue), but it is distributed over a larger spectrum. In ΔΣ-converters, noise is further reduced at low frequencies, which is the band where the signal of interest is, and it is increased at the higher frequencies, where it can be filtered. This technique is known as noise shaping.

For a first order delta sigma modulator, the noise is shaped by a filter with transfer function <math>\scriptstyle H_n(z) \,=\, \left[1 - z^{-1}\right] </math>. Assuming that the sampling frequency <math>\scriptstyle f_s \,\gg\, f_0</math>, the quantization noise in the desired signal bandwidth can be approximated as:

<math> \mathrm{n_0}\,=\, e_{rms}\frac{ \pi}{\sqrt{3}}\, (2f_0\tau)^{\frac{3}{2}} </math>.

Similarly for a second order delta sigma modulator, the noise is shaped by a filter with transfer function <math>\scriptstyle H_n(z) \,=\, \left[1 - z^{-1}\right]^2</math>. The in-band quantization noise can be approximated as:

<math>\mathrm{n_0}\,=\, e_{rms}\frac{ \pi^2}{\sqrt{5}}\, (2f_0\tau)^{\frac{5}{2}} </math>.

In general, for a <math>\scriptstyle \mathrm{N}</math>-order ΔΣ-modulator, the variance of the in-band quantization noise:

<math>\mathrm{n_0}\,=\, e_{rms}\frac{\pi^n}{\sqrt{2n + 1}}\, (2f_0\tau)^{\frac{2n + 1}{2}}</math>.

When the sampling frequency is doubled, the signal to quantization noise is improved by <math>\scriptstyle 10\log(2^{2N+1})\,dB </math> for a <math>\scriptstyle \mathrm{N}</math>-order ΔΣ-modulator. The higher the oversampling ratio, the higher the [[signal-to-noise ratio]] and the higher the resolution in bits.

Another key aspect given by oversampling is the speed/resolution tradeoff. In fact, the decimation filter put after the modulator not only filters the whole sampled signal in the band of interest (cutting the noise at higher frequencies), but also reduces the frequency of the signal increasing its resolution. This is obtained by a sort of ''averaging'' of the higher data rate bitstream.

=== Example of decimation ===
Let's have, for instance, an 8:1 decimation filter and a 1-bit bitstream; if we have an input stream like 10010110, counting the number of ones, we get 4. Then the decimation result is 4/8 = 0.5. We can then represent it with a 3-bits number 100 (binary), which means half of the largest possible number. In other words,
* the sample frequency is reduced by a factor of eight
* the serial (1-bit) input bus becomes a parallel (3-bits) output bus.

== Naming ==
The technique was first presented in the early 1960s by professor Haruhiko Yasuda while he was a student at Waseda University, Tokyo, Japan.{{Citation needed|date=May 2010}} The name ''Delta-Sigma'' comes directly from the presence of a Delta modulator and an integrator, as firstly introduced by Inose et al. in their patent application.<ref>H. Inose, Y. Yasuda, J. Murakami, "A Telemetering System by Code Manipulation -- ΔΣ Modulation", IRE Trans on Space Electronics and Telemetry, Sep. 1962, pp. 204-209.</ref> That is, the name comes from integrating or "''summing''" '''differences''', which are operations usually associated with Greek letters [[Sigma]] and [[Delta (letter)|Delta]] respectively. Both names ''Sigma-Delta'' and ''Delta-Sigma'' are frequently used.

== See also ==
* [[Pulse-density modulation]]
* [[Pulse-width modulation]]

==References==
{{Reflist}}
*{{cite web |title=ADC Architectures III: Sigma-Delta ADC Basics |author=Walt Kester |url=http://www.analog.com/static/imported-files/tutorials/MT-022.pdf |publisher=Analog Devices |date=October 2008 |format=PDF |accessdate=2010-11-02}}
*{{cite book |author=R. Jacob Baker |title=CMOS Mixed-Signal Circuit Design |url=http://CMOSedu.com/ |edition=2nd |publisher=Wiley-IEEE |isbn=978-0-470-29026-2 |year=2009}}
*{{cite book|author=R. Schreier, G. Temes|title=Understanding Delta-Sigma Data Converters|location=|publisher=|year=2005|pages=|isbn=0-471-46585-2}}
*{{cite book|author=S. Norsworthy, R. Schreier, G. Temes|title=Delta-Sigma Data Converters|location=|publisher=|year=1997|isbn=0-7803-1045-4}}
*{{cite book|author=J. Candy, G. Temes|title=Oversampling Delta-sigma Data Converters|location=|publisher=|year=1992|isbn=0-87942-285-8}}

== External links ==
{{Commons category|Signal processing}}
* [http://www.cs.tut.fi/sgn/arg/rosti/1-bit/ 1-bit A/D and D/A Converters]
* [http://www.embedded.com//showArticle.jhtml?articleID=22101730 Sigma-delta techniques extend DAC resolution] article by Tim Wescott 2004-06-23
* [http://www.commsdesign.com/design_corner/showArticle.jhtml?articleID=18402743 Tutorial on Designing Delta-Sigma Modulators: Part I] and [http://www.commsdesign.com/design_corner/showArticle.jhtml?articleID=18402763 Part II] by Mingliang (Michael) Liu
* [http://eecs.oregonstate.edu/research/members/temes/pubs.html Gabor Temes' Publications]
* [http://electronjunkie.wordpress.com/tag/sigma-delta-modulation/ Simple Sigma Delta Modulator example] Contains Block-diagrams, code, and simple explanations
* [http://www.circuitdesign.info/blog/2008/09/example-simulink-model-scripts/ Example Simulink model & scripts for continuous-time sigma-delta ADC] Contains example matlab code and Simulink model
* [http://www-cis.stanford.edu/icl/wooley-grp/projects.html Bruce Wooley's Delta-Sigma Converter Projects]
* [http://www.beis.de/Elektronik/DeltaSigma/DeltaSigma.html An Introduction to Delta Sigma Converters] (which covers both ADC's and DAC's sigma-delta)
* [http://www.maxim-ic.com/appnotes.cfm/an_pk/1870/CMP/WP-10 Demystifying Sigma-Delta ADCs]. This in-depth article covers the theory behind a Delta-Sigma analog-to-digital converter.
* [http://digitalsignallabs.com/SigmaDelta.pdf Motorola digital signal processors: Principles of sigma-delta modulation for analog-to-digital converters]
* [http://www.digitalsignallabs.com/presentation.pdf One-Bit Delta Sigma D/A Conversion Part I: Theory] article by Randy Yates presented at the 2004 comp.dsp conference
* [http://www.aholme.co.uk/Frac2/Mash.htm MASH (Multi-stAge noise SHaping) structure] with both theory and a block-level implementation of a MASH
* [http://www.techonline.com/learning/course/100152 How a Sigma-Delta ADC Works at TechOnline] free registration required to read the article
* [http://www.circuitdesign.info/blog/2008/11/continuous-time-sigma-delta-adc-noise-shaping-filter-circuit-architectures-2/ Continuous time sigma-delta ADC noise shaping filter circuit architectures] discusses architectural trade-offs for continuous-time sigma-delta noise-shaping filters
* [http://www.cardinalpeak.com/blog/?p=392/ Some intuitive motivation for why a Delta Sigma modulator works]

{{DEFAULTSORT:Delta-Sigma Modulation}}
[[Category:Digital signal processing]]

[[fr:Convertisseur analogique-numérique#Convertisseur Sigma Delta]]

Schrödinger equation

2006-11-11T23:13:13Z

142.177.181.146: /* Non-relativistic Schrödinger wave equation */

Transport Engineer Eure from Milton, has interests which includes caravaning, [http://www.rebelletest.co.za/?option=com_k2&view=itemlist&task=user&id=71737 big property developers in singapore] developers in singapore and riddles. In the previous year has made a visit to Curonian Spit.

Schrödinger equation

2006-11-11T23:12:50Z

142.177.181.146: /* Non-relativistic Schrödinger wave equation */

Crowning Singapore's tallest building and situated in the coronary heart of the brand new Central Business District, Clermont Residence defines new launch singapore property ([http://Www.Cadvb.nl/?option=com_k2&view=itemlist&task=user&id=101752 click through the next internet site]) heights of status with a limited assortment of only 181 unique apartments. Past the unparalleled views, residents will have the ability to get pleasure from 4 private amenity levels that provide privileged luxury. No. For the simple motive that if builders allowed that to happen, companies would not take on the job, as they'd have issue getting consumers to return by them. Additionally, you will be registered for the VIP Preview if you happen to so request. That sometimes involves submitting a type listing your particulars & most well-liked items, with your cheque. The agent will usually take care of a lot of the paperwork. Jurong Town Company Worldwide - It's mainly concerned in developing business properties in Singapore, together with development of factories, workshops, and warehouses. Executive Condominium bought under the Government Condominium Housing Scheme Act, 1996 any unit in a development offered under the manager condominium scheme. HLH Growth Pte Ltd If you end up the owner of a private apartment , you are a lessee below the 99 year lease the housing developer has created for each residence. You wouldn't personal any part of the widespread property - such because the automotive park or the pool - as these belong to the lessor, who can cost a separate price for using these facilities. As an residence proprietor you might have sure rights and obligations spelt out underneath the lease. However, you are not capable of participate within the administration of the amenities. At SLP International, our crew of pros is pushed to make sure our purchasers meet their business and investment goals. Under is a listing of some notable purchasers from completely different industries and markets, who have entrusted their real estate needs to the experience of SLP Worldwide. View our listing of Singapore's forty Richest.) But the challenge was a crowded market with massive boys like Far East Organization, Capital Land and a dozen others in the fray. To carve a definite id Garcha launched Elevation with a 3-pronged strategy. First, it will only deal in ground-level homes versus excessive-rise condominiums. Second, it could not construct and promote residential units but reasonably operate on a construct-personal-rent mannequin. Third, it might intention upscale. As far as I can see, the property market in Singapore looks to be reasonably steady in the subsequent couple of years, with no big crash in sight. Nonetheless, these banking on their HDB or non-prime shoebox models to go up significantly could also be upset. The measures implemented by the governments like low leverage and seller's stamp obligation will prevent any big property blowout ala US or Europe, and at the similar time slow down the market to prevent bubbles. On the identical time, interest costs will stay low for a while, but property investors will do nicely to put in buffers for his or her longer-term holdings as interest rates will not keep low forever. Cheng also revealted that TIEC Holdings had received a number of presents but chose to work with Teho because that they had a standard imaginative and prescient for the enterprise and consider the acquisition of an present property growth enterprise such as TIEC gives a jumpstart for Teho into the business. 'We have already got a team with a suite of experience in property development, and the business is running well. All we nee is powerful financial backing, and to ensure compliance with itemizing regulations," says Cheng." Wheelock Properties (Singapore) Limited, formerly often known as Marco Polo Developments Limited, was included in Singapore on 19th December 1972 and listed on the Singapore Alternate Securities Trading Restricted (SGX-ST) on sixth Could 1981. Its principal actions are that of property investor and developer, with a deal with luxurious residences. Complete the Sale - this can be a technical time period referring the fee of the contracted sale worth (from you as the Buyer) in alternate for the signed conveyance of title known as the "Instrument of Switch" which successfully transfers the ownership of the property from the present homeowners to yourself (as the new owner). Procedures for Purchase CABANA CLUSTER STRATA HOME SUNSHINE TERRACE, SINGAPORE (DISTRICT 26) The twin-key unit concept has been extra common with developers just lately because it has develop into a advertising strategy to attract traders. In the meanwhile costs of such units are nonetheless at a premium as the concept is relatively new. Nonetheless, seeing that this could be a norm in future developments, it might not create a surge in value transferring forward." - Eric Cheng; Group Chief Executive Officer of ECG Group of Companies Official plans for a major supply of recent homes over the following decade make the worth outlook even dimmer. But land costs have rallied, pushed up by international builders drawn by political and economic stability. Globalisation of commercial real property funding gathers pace in 2014 as transaction volumes up 23% in Q1 2014 Client Price Index

Schrödinger equation

2006-11-11T23:12:21Z

142.177.181.146: /* Non-relativistic Schrödinger wave equation */

Solicitor Broadbent from Deep River, has pastimes for example r/c cars, property developers in new launch singapore property ([http://Www.Cadvb.nl/?option=com_k2&view=itemlist&task=user&id=101752 click through the up coming page]) and dancing. Was in recent past visiting León Cathedral.

Schrödinger equation

2006-11-11T23:11:45Z

142.177.181.146: /* Non-relativistic Schrödinger wave equation */

In the event you have a look at the checklist of the Forbes forty richest folks in Singapore, you will note many who made their fortunes developing and investing in actual estate. Or just look around you – the average Singaporean's wealth probably comes more from the appreciation of his HDB flat or non-public property than from some other asset. SLA assists the Government in managing its land gross sales system. Our roles are to realize optimal returns from the sales of State lands and to appoint and manage the State's land sales brokers. The place land is slated for release through the Authorities tenders and auctions, we ensure that land is on the market and the land sale processes adjust to statutory tips. Misc. Franchise Resales Business For Sale, Promoting & Marketing Enterprise For Sale ACCOMPLICE WITH A EXTREMELY MOTIVATED CREW About our Business We are a global advertising and marketing enterprise who partners with an Award Profitable Management Improvement Company and are committed to becoming the chosen companion for people searching for their very own business alternative. Enterprise Des Tenure Any Freehold 999 Years ninety nine Years Protects the interests of property agents in addition to protecting the pursuits of members of the general public who have interaction the providers of property agents. 480 Toa Payoh Lorong 6, HDB Hub East Wing #08-02, Singapore 310480. For sale, buying and leasing within the major and secondary private residential markets. 30 Cecil Street, #20-03 Prudential Tower, Singapore 049712. Website with worth transaction data, value developments, properties and maps with each property itemizing. Can't discover what you want? Look at our comprehensive listing of flats in Singapore, introduction to model new apartment projects and countless assortment of property and condo footage. Semi-furnished condominium on the market # 528 sf Semi-furnished condominium on the market # 441 sf Expat Properties Wheelock Properties Select - Australia Buangkok (D19) Johor Iskandar Jurong (D22) Kallang (Singapore) Kovan (D19) London Newton (D11) [http://www.tajamterpercaya.com/blogs/viewstory/10726 tajamterpercaya.com] Novena (D11) Philippines, Manila Serangoon (D19) Higher Thomson (D20) I discovered the flat with the help of a property agent.' Profession improvement programmes, in-house valuation, auctions and administrative assist, undertaking advertising and marketing, skilled talks and traisning are constantly deliberate for the gross sales associates to assist them obtain better results for his or her clients while at Knight Frank Singapore. Actual estate brokers for getting, selling, leasing, and renting property. Runs abroad property initiatives for rental yeild and capital appreciation. How rates of interest have an effect on property prices How one can discover a good and reliable actual property agent Space of home or flat 8,000 homes near the American School. Jalan Kasau bungalow for rent at $eight,000 with 3 American households in a small subdivision of eight tons. A 5-min drive to the American School and 15-minute walk to the Kranji subway. Numerous greenery, no traffic and tranquility, but you don't get 500 children round this neighbourhood on Halloween's Day as you will, within the subdivision of Woodgrove Estate near the American Faculty. Leases have dropped significantly in 2003. Gross sales transaction volumes were expected to hit 4,000 units for 2012, near the combined EC sales volume in 2010 and 2011, in line with Savills Singapore. Nevertheless the last quarter was weak. In This autumn 2012, sales transactions had been 22.eight% down q-q to 7,931 models, in line with the URA. The quarterly sales discount was felt throughout the board. When the sale simply starts, I am not in a rush to buy. It is totally different from a non-public sale open for privileged clients for at some point solely. Orchard / Holland (D09-10) Condominium For Sale The Tembusu is a singular large freehold land outside the central area. Designed by a number of award-winning architects Arc Studio Architecture + Urbanism, the development is targeted for launch in mid 2013. Submit your Property Condos Near MRT