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• FMA4 is supported in AMD processors starting with Bulldozer architecture. FMA4 was realized in hardware before FMA3.
• FMA3 is supported in AMD processors starting with Piledriver architecture and Intel starting with Haswell processors and will be supported by Broadwell processors in 2014.

New instructions

The FMA3 and FMA4 instruction sets have almost identical functionality but are not mutually compatible. Both contain fused multiply–add (FMA) instructions for floating point scalar and SIMD operations. It will take some time for the compiler creators to support the differences and to optimize code accordingly.

Compatibility issue

The difference between FMA3 and FMA4 concerns the issue of whether the instruction can have three or four different operands. The FMA operation has the form:

$d=a+b\times c$

The 4-operand form (FMA4) allows a, b, c and d to be four different registers, while the 3-operand form (FMA3) requires that d is the same register as either a, b or c. The 3-operand form makes the code shorter and the hardware implementation slightly simpler while the 4-operand form provides more programming flexibility.

See XOP instruction set for more discussion of compatibility issues between Intel and AMD.

FMA3 instruction set

CPUs with FMA3

• Intel
  • Intel introduced hardware FMA in processors based on Haswell (microarchitecture) during 2013.
• AMD
  • AMD introduced FMA3 support in processors starting with Piledriver architecture for compatibility reasons. The 2nd generation APU processors based on "Trinity" (32nm) supporting FMA3 instructions were launched May 15, 2012. The 2nd generation Bulldozer processors with Piledriver cores supporting FMA3 instructions were launched October 23, 2012.

Excerpt from FMA3

Mnemonic (AT&T)	Operands	Operation
VFMADD132PDy	ymm, ymm, ymm/m256	$0 = $0×$2 + $1
VFMADD132PSy
VFMADD132PDx	xmm, xmm, xmm/m128
VFMADD132PSx
VFMADD132SD	xmm, xmm, xmm/m64
VFMADD132SS	xmm, xmm, xmm/m32
VFMADD213PDy	ymm, ymm, ymm/m256	$0 = $1×$0 + $2
VFMADD213PSy
VFMADD213PDx	xmm, xmm, xmm/m128
VFMADD213PSx
VFMADD213SD	xmm, xmm, xmm/m64
VFMADD213SS	xmm, xmm, xmm/m32
VFMADD231PDy	ymm, ymm, ymm/m256	$0 = $1×$2 + $0
VFMADD231PSy
VFMADD231PDx	xmm, xmm, xmm/m128
VFMADD231PSx
VFMADD231SD	xmm, xmm, xmm/m64
VFMADD231SS	xmm, xmm, xmm/m32

FMA4 instruction set

CPUs with FMA4

• AMD
  • Bulldozer processor core, launched October 12, 2011.
  • Piledriver
• Intel
  • It is uncertain whether future Intel processors will support FMA4, due to Intel's announced change to FMA3.

Excerpt from FMA4

Mnemonic (AT&T)	Operands	Operation
VFMADDPDx	xmm, xmm, xmm/m128, xmm/m128	$0 = $1×$2 + $3
VFMADDPDy	ymm, ymm, ymm/m256, ymm/m256
VFMADDPSx	xmm, xmm, xmm/m128, xmm/m128
VFMADDPSy	ymm, ymm, ymm/m256, ymm/m256
VFMADDSD	xmm, xmm, xmm/m64, xmm/m64
VFMADDSS	xmm, xmm, xmm/m32, xmm/m32

History

The incompatibility between Intel's FMA3 and AMD's FMA4 is due to both companies changing plans without coordinating coding details with each other. AMD changed their plans from FMA3 to FMA4 while Intel changed their plans from FMA4 to FMA3 almost at the same time. The history can be summarized as follows:

• August 2007: AMD announces the SSE5 instruction set, which includes 3-operand FMA instructions. A new coding scheme (DREX) is introduced for allowing instructions to have three operands.
• April 2008: Intel announces their AVX and FMA instruction sets, including 4-operand FMA instructions. The coding of these instructions uses the new VEX coding scheme which is more flexible than AMD's DREX scheme. (Section requires an actual source, Intel sources are not acceptable for debatable specifics.)
• December 2008: Intel changes the specification for their FMA instructions from 4-operand to 3-operand instructions. The VEX coding scheme is still used.
• May 2009: AMD changes the specification of their FMA instructions from the 3-operand DREX form to the 4-operand VEX form, compatible with the April 2008 Intel specification rather than the December 2008 Intel specification.
• October 2011: AMD Bulldozer processor supports FMA4.
• January 2012: AMD announces FMA3 support in future processors codenamed Trinity and Vishera; they are based on the Piledriver architecture.
• May 2012: AMD Piledriver processor supports both FMA3 and FMA4.
• June 2013: Intel Haswell processor supports FMA3.

It is currently uncertain whether the 3-operand VEX coded form (here called FMA3) or the 4-operand form (FMA4) will be the dominating standard in the future.

Compiler and assembler support

Different compilers provide different levels of support for FMA4:

• GCC supports FMA4 with -mfma4 since version 4.5.0 and FMA3 with -mfma since version 4.7.0.
• Microsoft Visual C++ 2010 SP1 supports FMA4 instructions.
• Microsoft Visual C++ 2012 supports FMA3 instructions.
• PathScale supports FMA4 with -mfma.
• Open64 5.0 adds "limited support".
• Intel compilers support only FMA3 instructions.
• NASM supports FMA3 instructions since version 2.03 and FMA4 instructions since 2.06.
• YAsm supports FMA3 and FMA4 instructions since version 1.1.0.
• FASM supports both FMA3 and FMA4 instructions.

References

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