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| '''Rent's rule''' pertains to the organization of computing logic, specifically the relationship between the number of external signal connections to a logic block (i.e., the number of "pins") with the number of logic gates in the logic block, and has been applied to circuits ranging from small digital circuits to mainframe computers.
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| == E.F. Rent's discovery and first publications ==
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| In the 1960s, E.F. Rent, an [[IBM]] employee, found a remarkable trend between the number of pins (terminals T) at the boundaries of [[integrated circuit]] designs at [[IBM]] and the number of internal components (g), such as logic gates or standard cells. On a log-log plot, these datapoints were on a straight line, implying a power-law relation <math>T = t g^p</math> where t and p are constants (p < 1.0, and generally 0.5 < p < 0.8).
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| Rent disclosed his findings in [[IBM]]-internal memoranda that were published in the IBM Journal of Research and Development in 2005 (IBM J. Res. & Dev. Vol. 49, No. 4/5 July/September 2005, pp. 777–803), but the relation was described in 1971 by Landman and Russo.<ref name="LandmanRusso">B. S. Landman and R. L. Russo, [http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1671752 On a Pin Versus Block Relationship For Partitions of Logic Graphs], IEEE Trans. on Comput., col. C-20, pp. 1469-1479, 1971. </ref> They performed a hierarchical circuit partitioning in such a way that at each hierarchical level (top-down) the least number of interconnections had to be cut to partition the circuit (in more or less equal parts). At each partitioning step, they noted the number of terminals and the number of components in each partition and then partitioned the sub-partitions further. They found the power law rule applied to the resulting T versus g plot and named it "Rent's rule".
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| It is crucial to recognise that Rent's rule is an empirical result based on observations of existing designs, and therefore it is less applicable to the analysis of non-traditional circuit architectures. Having said that, it does provide a useful framework with which to compare similar architectures.
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| == Theoretical basis ==
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| Christie and Stroobandt<ref>P. Christie and D. Stroobandt, {{doi-inline|10.1109/92.902258|The Interpretation and Application of Rent's Rule}}, IEEE Trans. on VLSI Systems, Special Issue on
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| System-Level Interconnect Prediction, vol. 8, no. 6, pp. 639-648, 2000.
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| </ref> later derived Rent's rule theoretically
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| for homogeneous systems and pointed out that the amount of optimization
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| achieved in [[Placement (EDA)|placement]] is reflected by the parameter <math>p</math>,
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| the "Rent exponent", which also depends on the circuit topology. In particular, values
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| <math>p<1</math> correspond to a greater fraction of short interconnects.
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| The constant <math>t</math> in Rent's rule can be viewed as the average number
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| of terminals required by a single logic block since <math>T = t</math>
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| when <math>g = 1</math>.
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| == Special cases and applications ==
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| Random arrangement of logic blocks typically have <math>p=1</math>.
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| Larger values are impossible since the maximum number of terminals
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| for any region containing g logic components in a homogeneous system is | |
| given by <math>T = t g</math>. Lower bounds on p depend on the interconnection
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| topology since it is generally impossible to make all wires short.
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| This lower bound <math>p*</math> is often called the "intrinsic Rent exponent",
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| a notion first introduced by Hagen et al.<ref>L. Hagen, A. B. Kahng, F. J. Kurdahi and C. Ramachandran, {{doi-inline|10.1109/43.273752|On the Intrinsic Rent Parameter and Spectra-based Partitioning Methodologies}}, IEEE Trans. on Comput.-Aided Des., Integrated
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| Circuits \& Syst., vol. 13, no. 1, pages 27 - 37, 1994.
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| </ref> It can be used to characterize
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| optimal placements and also measure the interconnection complexity
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| of a circuit. Higher (intrinsic) Rent exponent values correspond
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| to a higher topological complexity. One extreme example (<math>p=0</math>)
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| is a long chain of logic blocks, while a [[Clique (graph theory)|clique]] has <math>p=1</math>.
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| In realistic 2D circuits, <math>p*</math> ranges from 0.5 for
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| highly-regular circuits (such as [[Static random access memory|SRAM]])
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| to 0.75 for random logic.<ref>R. L. Russo, On the Tradeoff Between Logic Performance and
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| Circuit-to-Pin Ratio for LSI, IEEE Trans. Comput., vol. C - 21,
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| pages 147 - 153, 1972.
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| </ref>
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| System performance analysis tools such as [[BACPAC]] typically use Rent's rule to calculate expected wiring lengths and wiring demands.
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| == Estimating Rent's exponent ==
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| To estimate Rent's exponent, one can use top-down partitioning,
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| as used in min-cut placement. For every partition, count
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| the number of terminals connected to the partition and
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| compare it to the number of logic blocks in the partition.
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| Rent's exponent can then be found by fitting these datapoints
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| on a log-log plot, resulting in an exponent p'.
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| For optimally partitioned circuits, <math>p' = p*</math>
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| but this is no longer the case for practical (heuristic)
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| partitioning approaches. For partitioning-based placement
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| algorithms <math>p^* \leq p' \leq p</math>.<ref>P. Verplaetse, J. Dambre, D. Stroobandt, and J. Van Campenhout, {{doi-inline|10.1145/368640.368665|On Partitioning vs. Placement Rent Properties}}, Intl. Workshop on
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| System-Level Interconnect Prediction (SLIP 2001), pp. 33 - 40, March 2001.
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| </ref>
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| == Region II of Rent's rule ==
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| Landman and Russo found a deviation of Rent's rule near the
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| "far end", i.e., for partitions with a large number of blocks, which is
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| known as "Region II" of Rent's Rule.<ref name="LandmanRusso" /> A similar deviation exists at
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| for small partitions, and has been found by Stroobandt<ref>D. Stroobandt, {{doi-inline|10.1109/GLSV.1999.757445|On an efficient method for estimating the interconnection complexity of designs and on the existence of region III in Rent's rule}}, Proc. 9th Great Lakes Symposium on VLSI, pp. 330 - 331, 1999.
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| </ref> who called it Region III.
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| == Rentian wirelength estimation ==
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| Another [[IBM]] employee, Donath, discovered that Rent's rule can be used
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| to estimate the average wirelength and the wirelength distribution
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| in [[VLSI]] chips.<ref>W. E. Donath, [http://ieeexplore.ieee.org/search/wrapper.jsp?arnumber=1084635 Placement and Average Interconnection Lengths of Computer Logic], IEEE Trans. Circuits & Syst., vol. CAS-26, pp. 272 - 277, 1979.
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| </ref><ref>W. E. Donath, [http://www.research.ibm.com/journal/rd/252/ibmrd2502a3H.pdf Wire Length Distribution for Placements of Computer Logic], IBM J. of Research and Development, vol. 25, pp. 152 - 155, 1981.
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| </ref>
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| This motivated the System Level Interconnect Prediction
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| workshop, founded in 1999, and an entire community working
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| on wirelength prediction (see a survey by Stroobandt<ref name=Stroobandt>
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| D. Stroobandt, ''A Priori Wire Length Estimates for Digital Design''.
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| Kluwer Academic Publishers. ISBN 0-7923-7360-X. 2001. pp. 298.
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| </ref>). The resulting
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| wirelength estimates have been improved significantly since
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| then and are now used for "technology exploration."<ref>A. E. Caldwell, Y. Cao, A. B. Kahng, F. Koushanfar, H. Lu, I. L. Markov,
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| M. Oliver, D. Stroobandt, and D. Sylvester, {{doi-inline|10.1145/337292.337617|GTX: The MARCO GSRC Technology Extrapolation System}}, IEEE/ACM Design Automation Conf., pp. 693 - 698, June 2000.
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| </ref>
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| The use of Rent's rule allows to perform such estimates ''a priori''
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| (i.e., before actual placement) and thus predict the properties
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| of future technologies (clock frequencies, number of routing layers needed,
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| area, power) based on limited information about future circuits and
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| technologies.
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| A comprehensive overview of work based on Rent's rule has been published by Stroobandt.<ref name=Stroobandt/>
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| <ref>
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| D. Stroobandt, Recent Advances in System-Level Interconnect
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| Prediction, IEEE Circuits and Systems Society Newsletter,
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| vol. 11, no. 4, pages 1; 4-20; 48, December 2000. Invited.
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| Available at http://www.nd.edu/~stjoseph/newscas/.
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| </ref>
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| == See also ==
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| *[[Electronic design automation]]
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| *[[Integrated circuit design]]
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| == References ==
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| <references/>
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| [[Category:Gate arrays]]
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| [[Category:Electronic design automation]]
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