|
|
| Line 1: |
Line 1: |
| In electronics, an '''adder''' or '''summer''' is a [[digital circuit]] that performs [[addition]] of numbers.
| | [http://browse.deviantart.com/?q=Roberto Roberto] is what's written over his birth certificate fortunately he never really enjoyed reading that name. South Carolina is your birth place. The favourite hobby for him and as well his kids is to assist you fish and he's been for a while doing it for a very long time. Auditing is how he supports or perhaps family. Go of his website to hit upon out more: http://[https://Www.Flickr.com/search/?q=circuspartypanama circuspartypanama].com<br><br> |
| In many [[computer]]s and other kinds of processors, adders are used not only in the [[arithmetic logic unit]](s), but also in other parts of the processor, where they are used to calculate addresses, table indices, and similar operations.
| |
|
| |
|
| Although adders can be constructed for many numerical representations, such as [[binary-coded decimal]] or [[excess-3]], the most common adders operate on [[binary numeral system|binary]] numbers.
| | my web blog [http://circuspartypanama.com Clash of clans cheats] |
| In cases where [[two's complement]] or [[ones' complement]] is being used to represent negative numbers, it is trivial to modify an adder into an [[adder–subtractor]].
| |
| Other [[signed number representations]] require a more complex adder.
| |
| | |
| ==Half adder==
| |
| | |
| [[File:half Adder.svg|right|thumb|Half adder logic diagram]] The '''half adder''' adds two single binary digits ''A'' and ''B''. It has two outputs, sum (''S'') and carry (''C''). The carry signal represents an overflow into the next digit of a multi-digit addition. The value of the sum is {{nobreak|2''C'' + ''S''}}. The simplest half-adder design, pictured on the right, incorporates an [[XOR gate]] for ''S'' and an [[AND gate]] for ''C''. With the addition of an OR gate to combine their carry outputs, two half adders can be combined to make a full adder.<ref>
| |
| {{cite book
| |
| | title = Excel HSC Software Design and Development'''
| |
| | author = Geoffrey A. Lancaster
| |
| | publisher = Pascal Press
| |
| | year = 2004
| |
| | isbn = 9781741251753
| |
| | page = 180
| |
| | url = http://books.google.com/books?id=PZkDpS4m0fMC&pg=PA180
| |
| }}</ref>
| |
| The half-adder adds two input bits and generate carry and sum which are the two outputs of half-adder.The input variables of a Half adder are called the Augend and addend bits.The output variables are the Sum and Carry.The Truth table for the Half adder is :
| |
| | |
| {| class="wikitable" style="text-align:center"
| |
| |-
| |
| !colspan="2"| Inputs !!colspan="2"| Outputs
| |
| |-
| |
| ! ''A'' !! ''B'' !! ''S'' !! ''C''
| |
| |-
| |
| | 0 || 0 || 0 || 0
| |
| |-
| |
| | 1 || 0 || 1 || 0
| |
| |-
| |
| | 0 || 1 || 1 || 0
| |
| |-
| |
| | 1 || 1 || 0 || 1
| |
| |-
| |
| |}
| |
| | |
| ==Full adder==
| |
| | |
| [[File:1-bit full-adder.svg|thumb|right|Schematic symbol for a 1-bit full adder with ''C''<sub>in</sub> and ''C''<sub>out</sub> drawn on sides of block to emphasize their use in a multi-bit adder]]
| |
| | |
| A '''full adder''' adds binary numbers and accounts for values carried in as well as out. A one-bit full adder adds three one-bit numbers, often written as ''A'', ''B'', and ''C''<sub>in</sub>; ''A'' and ''B'' are the operands, and ''C''<sub>in</sub> is a bit carried in from the next less significant stage.<ref name=Mano79>M. Morris Mano, ''Digital Logic and Computer Design'', Prentice-Hall 1979, ISBN 0-13-21450-3 pp.119-123</ref> The full-adder is usually a component in a cascade of adders, which add 8, 16, 32, etc. bit binary numbers. The circuit produces a two-bit output, output carry and sum typically represented by the signals ''C''<sub>out</sub> and ''S'', where <math>\mathrm{sum} = 2 \times C_{out} + S</math>. The one-bit full adder's [[truth table]] is:
| |
| | |
| [[File:Full Adder.svg|thumb|right|Full-adder logic diagram]]
| |
| | |
| {| class="wikitable" style="text-align:center"
| |
| |-
| |
| !colspan="3"| Inputs !!colspan="2"| Outputs
| |
| |-
| |
| ! ''A'' !! ''B'' !! ''C''<sub>in</sub> !! ''C''<sub>out</sub> !! ''S''
| |
| |-
| |
| | 0 || 0 || 0 || 0 || 0
| |
| |-
| |
| | 1 || 0 || 0 || 0 || 1
| |
| |-
| |
| | 0 || 1 || 0 || 0 || 1
| |
| |-
| |
| | 1 || 1 || 0 || 1 || 0
| |
| |-
| |
| | 0 || 0 || 1 || 0 || 1
| |
| |-
| |
| | 1 || 0 || 1 || 1 || 0
| |
| |-
| |
| | 0 || 1 || 1 || 1 || 0
| |
| |-
| |
| | 1 || 1 || 1 || 1 || 1
| |
| |}
| |
| | |
| A full adder can be implemented in many different ways such as with a custom [[transistor]]-level circuit or composed of other gates. One example implementation is with <math>S = A \oplus B \oplus C_{in}</math> and <math>C_{out} = (A \cdot B) + (C_{in} \cdot (A + B))</math>.
| |
| | |
| In this implementation, the final [[OR gate]] before the carry-out output may be replaced by an [[XOR gate]] without altering the resulting logic. Using only two types of gates is convenient if the circuit is being implemented using simple IC chips which contain only one gate type per chip. In this light, C<sub>out</sub> can be implemented as <math>C_{out} = (A \cdot B) + (C_{in} \cdot (A \oplus B))</math>.
| |
| | |
| A full adder can be constructed from two half adders by connecting ''A'' and ''B'' to the input of one half adder, connecting the sum from that to an input to the second adder, connecting ''C<sub>i</sub>'' to the other input and OR the two carry outputs. Equivalently, ''S'' could be made the three-bit XOR of ''A'', ''B'', and ''C<sub>i</sub>'', and ''C<sub>out</sub>'' could be made the three-bit [[majority function]] of ''A'', ''B'', and ''C<sub>in</sub>''.
| |
| | |
| ==More complex adders==
| |
| | |
| ===Ripple-carry adder===
| |
| | |
| [[File:4-bit ripple carry adder.svg|thumb|right|4-bit adder with logic gates shown]]
| |
| | |
| It is possible to create a logical circuit using multiple full adders to add ''N''-bit numbers. Each full adder inputs a ''C<sub>in</sub>'', which is the ''C<sub>out</sub>'' of the previous adder. This kind of adder is called a ''ripple-carry adder'', since each carry bit "ripples" to the next full adder. Note that the first (and only the first) full adder may be replaced by a half adder.
| |
| | |
| The layout of a ripple-carry adder is simple, which allows for fast design time; however, the ripple-carry adder is relatively slow, since each full adder must wait for the carry bit to be calculated from the previous full adder.
| |
| The [[gate delay]] can easily be calculated by inspection of the full adder circuit.
| |
| Each full adder requires three levels of logic. In a 32-bit ripple-carry adder, there are 32 full adders, so the critical path (worst case) delay is 2 (from input to carry in first adder) + 31 * 2 (for carry propagation in later adders) = 64 gate delays. A design with alternating carry polarities and optimized [[AND-OR-Invert]] gates can be about twice as fast.<ref>{{cite conference
| |
| | conference = 20th IEEE Symposium on Computer Arithmetic
| |
| | title = Fast Ripple-Carry Adders in Standard-Cell CMOS VLSI
| |
| | author = Burgess, N.
| |
| | pages = 103–111
| |
| | year = 2011
| |
| | url = http://ieeexplore.ieee.org/Xplore/login.jsp?url=http%3A%2F%2Fieeexplore.ieee.org%2Fiel5%2F5991607%2F5992089%2F05992115.pdf%3Farnumber%3D5992115&authDecision=-203
| |
| }}</ref>
| |
| | |
| ===Carry-lookahead adders===
| |
| {{main|Carry-lookahead adder}}
| |
| | |
| [[File:4-bit carry lookahead adder.svg|thumb|right|4-bit adder with carry lookahead]]
| |
| | |
| To reduce the computation time, engineers devised faster ways to add two binary numbers by using [[carry-lookahead adder]]s.
| |
| They work by creating two signals (''P'' and ''G'') for each bit position, based on whether a carry is propagated through from a less significant bit position (at least one input is a '1'), generated in that bit position (both inputs are '1'), or killed in that bit position (both inputs are '0'). In most cases, ''P'' is simply the sum output of a half-adder and ''G'' is the carry output of the same adder. After ''P'' and ''G'' are generated the carries for every bit position are created. Some advanced carry-lookahead architectures are the [[Manchester carry chain]], [[Brent–Kung adder]], and the [[Kogge–Stone adder]].
| |
| | |
| Some other multi-bit adder architectures break the adder into blocks. It is possible to vary the length of these blocks based on the [[propagation delay]] of the circuits to optimize computation time. These block based adders include the [[carry-skip adder|carry-skip (or carry-bypass) adder]] which will determine ''P'' and ''G'' values for each block rather than each bit, and the [[carry select adder]] which pre-generates the sum and carry values for either possible carry input (0 or 1) to the block, using multiplexers to select the appropriate result ''when'' the carry bit is known.
| |
| | |
| Other adder designs include the [[carry-select adder]], [[conditional sum adder]], [[carry-skip adder]], and [[carry-complete adder]].
| |
| | |
| ===Lookahead carry unit===
| |
| | |
| [[File:64-bit lookahead carry unit.svg|thumb|right|A 64-bit adder]]
| |
| | |
| By combining multiple carry lookahead adders even larger adders can be created.
| |
| This can be used at multiple levels to make even larger adders.
| |
| For example, the following adder is a 64-bit adder that uses four 16-bit CLAs with two levels of LCUs.
| |
| | |
| ===Carry-save Adders===
| |
| {{main|Carry-save adder}}
| |
| | |
| If an adding circuit is to compute the sum of three or more numbers it can be advantageous to not propagate the carry result. Instead, three input adders are used, generating two results: a sum and a carry. The sum and the carry may be fed into two inputs of the subsequent 3-number adder without having to wait for propagation of a carry signal. After all stages of addition, however, a conventional adder (such as the ripple carry or the lookahead) must be used to combine the final sum and carry results.
| |
| | |
| ==3:2 compressors==
| |
| | |
| We can view a full adder as a ''3:2 lossy compressor'': it sums three one-bit inputs, and returns the result as a single two-bit number; that is, it maps 8 input values to 4 output values. Thus, for example, a binary input of ''101'' results in an output of ''1+0+1=10'' (decimal number '2'). The carry-out represents bit one of the result, while the sum represents bit zero. Likewise, a half adder can be used as a ''2:2 lossy compressor'', compressing four possible inputs into three possible outputs.
| |
| | |
| Such compressors can be used to speed up the summation of three or more addends. If the addends are exactly three, the layout is known as the [[carry-save adder]]. If the addends are four or more, more than one layer of compressors is necessary and there are various possible design for the circuit: the most common are [[Dadda tree|Dadda]] and [[Wallace tree]]s. This kind of circuit is most notably used in multipliers, which is why these circuits are also known as Dadda and Wallace multipliers.
| |
| | |
| ==References==
| |
| <references/>
| |
| | |
| ==External links==
| |
| * [http://www.aoki.ecei.tohoku.ac.jp/arith/mg/algorithm.html Hardware algorithms for arithmetic modules], includes description of several adder layouts with figures.
| |
| * [http://dev.code.ultimater.net/electronics/8-bit-full-adder-and-subtractor/ 8-bit Full Adder and Subtractor], a demonstration of an interactive Full Adder built in JavaScript solely for learning purposes.
| |
| * [http://teahlab.com/Full_Adder/ Interactive Full Adder Simulation], Interactive Full Adder circuit constructed with Teahlab's online circuit simulator.
| |
| * [http://teahlab.com/Half_Adder/ Interactive Half Adder Simulation], Half Adder circuit built with Teahlab's circuit simulator.
| |
| * [http://www.edaplayground.com/s/example/368 4-bit Full Adder Simulation] built in Verilog, and the accompanying [http://www.youtube.com/watch?v=bL3ihMA8_Gs&hd=1 Ripple Carry Full Adder Video Tutorial]
| |
| | |
| {{DEFAULTSORT:Adder (Electronics)}}
| |
| [[Category:Computer arithmetic]]
| |
| [[Category:Adders| ]]
| |
| [[Category:Binary logic]]
| |
Roberto is what's written over his birth certificate fortunately he never really enjoyed reading that name. South Carolina is your birth place. The favourite hobby for him and as well his kids is to assist you fish and he's been for a while doing it for a very long time. Auditing is how he supports or perhaps family. Go of his website to hit upon out more: http://circuspartypanama.com
my web blog Clash of clans cheats