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| | The writer's title is Andera and she believes it sounds quite great. Some time in the past she chose to reside in Alaska and her parents reside nearby. Credit authorising is how she tends to make a living. Doing ballet is something she would by no means give up.<br><br>Also visit my page :: best psychic readings ([http://appin.co.kr/board_Zqtv22/688025 appin.co.kr]) |
| In [[computer architecture]], '''cycles per instruction''' (aka '''clock cycles per instruction''', '''clocks per instruction''', or '''CPI''') is one aspect of a [[central processing unit|processor's]] performance: the average number of [[clock cycle]]s per [[Instruction (computer science)|instruction]] for a program or program fragment.<ref>{{cite book |title=Computer Organization and Design: The Hardware/Software Interface|first=David A.|last1=Patterson|first2=John L.|last2=Hennessy|}}</ref> It is the [[multiplicative inverse]] of [[instructions per cycle]].
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| ==Definition==
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| Cycles Per Instruction is defined by the following:
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| <math>
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| CPI = \frac{\Sigma (IIC)(CCI) }{IC}
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| </math>
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| Where '''IIC''' is the number of instructions for a given instruction type, '''CCI''' is the clock-cycles for a given instruction type, '''IC''' is the total instruction count. The summation sums over all instruction types for a given benchmarking process.
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| ==Explanation==
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| Let us assume a [[classic RISC pipeline]], with the following 5 stages:
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| # Instruction fetch cycle (IF)
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| # Instruction decode/Register fetch cycle (ID)
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| # Execution/Effective address cycle (EX)
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| # Memory access (MEM)
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| # Write-back cycle (WB)
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| Each stage requires one clock cycle and an instruction passes through the stages sequentially. Without [[pipelining]], a new instruction is fetched in stage 1 only after the previous instruction finishes at stage 5. Therefore without pipelining the number of cycles it takes to execute an instruction is 5. This is the definition of CPI.
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| With pipelining we can improve the CPI by exploiting [[instruction level parallelism]]. For example, what if an instruction is fetched every cycle? We could theoretically have 5 instructions in the 5 pipeline stages at once (one instruction per stage). In this case, a different instruction would complete stage 5 in every clock cycle, and therefore on average we have one clock cycle per instruction (CPI = 1).
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| With a single-issue processor, the best CPI attainable is 1. However with multiple-issue processors, we may achieve even better CPI values. For example a processor that issues two instructions per clock cycle (see [[Superscalar]]) can achieve a CPI of 0.5 when two instructions are completing every clock cycle.
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| ==Examples==
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| === Example 1 ===
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| For the multi-cycle [[MIPS architecture|MIPS]], there are 5 types of instructions:
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| * Load (5 cycles)
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| * Store (4 cycles)
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| * [[MIPS architecture#MIPS assembly language|R-type]] (4 cycles)
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| * [[MIPS architecture#MIPS assembly language|Branch]] (3 cycles)
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| * [[MIPS architecture#MIPS assembly language|Jump]] (3 cycles)
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| If a program has:
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| * 50% R-type instructions
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| * 15% load instructions
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| * 25% store instructions
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| * 8% branch instructions
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| * 2% jump instructions
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| then, the CPI is:
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| <math>
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| \text{CPI} = \frac{4 \times 50 + 5 \times 15 + 4 \times 25 + 3 \times 8 + 3 \times 2}{100} = 4.05
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| </math> | |
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| ===Example 2===
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| <ref>Advanced Computer Architecture by Kai Hwang, Chapter 1, Exercise Problem 1.1</ref> A 400-[[MHz]] processor was used to execute a [[benchmark program]] with the following [[instruction mix]] and [[clock cycle]] count: | |
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| {| class="wikitable"
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| |-
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| ! Instruction type
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| ! Instruction count
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| ! Clock cycle count
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|
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| |-
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| | Integer arithmetic
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| | 45000
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| | 1
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| |-
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| | Data transfer
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| | 32000
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| | 2
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| |-
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| | Floating point
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| | 15000
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| | 2
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| |-
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| | Control transfer
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| | 8000
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| | 2
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| |}
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| Determine the effective CPI, [[Instructions per second#Million instructions per second|MIPS]] rate, and execution time for this program.
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| : Total instruction count = 100000
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| <math>
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| \text{CPI} = \frac{45000 \times 1 + 32000 \times 2 + 15000 \times 2 + 8000 \times 2}{100000} = \frac{155000}{100000} = 1.55
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| </math>
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| <math>
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| \text{Effective processor performance} = \text{MIPS} = \frac{\text{clock frequency}}{\text{CPI} \times 1000000} = \frac{400 \times 1000000}{1.55 \times 1000000} = 258 \, \text{MIPS}
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| </math>
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| Therefore:
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| <math>
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| \text{Execution time}(T) = \text{CPI} \times \text{Instruction count} \times \text{clock time} = \frac{\text{CPI} \times \text{Instruction count}}{\text{frequency}} = \frac{1.55 \times 100000}{400 \times 1000000} = \frac{1.55}{4000} = 0.387 \, \text{ms}
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| </math>
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| ==See also==
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| *[[MIPS]]
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| * [[Instructions per cycle]] (IPC)
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| * [[Instructions per second]] (IPS)
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| * [[Cycle per second]] ([[Hertz|Hz]])
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| * [[Megahertz myth]]
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| * The [[Benchmark (computing)|benchmark]] article provides a useful introduction to computer performance measurement for those readers interested in the topic.
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| ==References==
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| {{Reflist}}
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| {{DEFAULTSORT:Cycles Per Instruction}}
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| [[Category:Instruction processing]]
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| [[Category:Clock signal]]
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