Homomorphic encryption: Difference between revisions

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m per WP:HYPHEN, sub-subsection 3, points 3,4,5, replaced: fully- → fully (5), nearly- → nearly, typo(s) fixed: of of → of (2) using AWB
 
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A '''switched capacitor''' is an [[electronic circuit]] element used for [[Discrete signal|discrete time]] [[signal processing]]. It works by moving charges into and out of capacitors when [[switch]]es are opened and closed. Usually, non-overlapping signals are used to control the switches, so that not all switches are closed simultaneously. [[Electronic filter|Filter]]s implemented with these elements are termed "switched-capacitor filters,"  and depend only on the ratios between capacitances. This makes them much more suitable for use within [[integrated circuit]]s, where accurately specified resistors and capacitors are not economical to construct.<ref>[http://www.swarthmore.edu/NatSci/echeeve1/Ref/FilterBkgrnd/SwitchedCap.html ''Switched Capacitor Circuits''], Swarthmore College course notes, accessed 2009-05-02</ref>
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== The switched capacitor resistor ==
[[Image:Switching capacitor schematic.PNG|right|thumb|Switched-capacitor resistor]]
The simplest switched capacitor (SC) circuit is the switched capacitor resistor, made of one capacitor C and two switches S{{sub|1}} and S{{sub|2}} which connect the capacitor with a given frequency alternately to the input and output of the SC. Each switching cycle transfers a charge <math>q</math> from the input to the output at the switching frequency <math>f</math>. Recall that the charge ''q'' on a capacitor ''C'' with a voltage ''V'' between the plates is given by:
:<math>q = CV\ </math>
where ''V'' is the voltage across the capacitor. Therefore, when S{{sub|1}} is closed while S{{sub|2}} is open, the charge stored in the capacitor C{{sub|S}} is:
:<math>q_{\text{IN}} = C_S V_{\text{IN}}.\ </math>
When S{{sub|2}} is closed, some of that charge is transferred out of the capacitor, after which the charge that remains in capacitor C{{sub|S}} is:
:<math>q_{\text{OUT}} = C_S V_{\text{OUT}}.\ </math>
Thus, the charge moved out of the capacitor to the output is:
:<math>q = q_{\text{IN}}-q_{\text{OUT}} = C_S(V_{\text{IN}}-V_{\text{OUT}})\ </math>
Because this charge ''q'' is transferred at a rate ''f'', the rate of transfer of charge per unit time is:
:<math>I = qf.\ </math>
Note that we use ''I'', the symbol for electric current, for this quantity. This is to demonstrate that a continuous transfer of charge from one node to another is equivalent to a current. Substituting for ''q'' in the above, we have:
:<math>I = C_S(V_{\text{IN}}-V_{\text{OUT}})f\ </math>
Let ''V'' be the voltage across the SC from input to output. So:
:<math>V = V_{\text{IN}} - V_{\text{OUT}}.\ </math>
So the equivalent resistance ''R'' (i.e., the voltage&ndash;current relationship) is:
:<math>R = {V \over I} = {1 \over {C_S f}}.\ </math>
Thus, the SC behaves like a [[resistor]] whose value depends on capacitance ''C{{sub|S}}'' and switching frequency ''f''.  
 
The SC resistor is used as a replacement for simple resistors in [[integrated circuit]]s because it is easier to fabricate reliably with a wide range of values. It also has the benefit that its value can be adjusted by changing the switching frequency (i.e., it is a programmable resistance). See also: [[operational amplifier applications]].
<math>q = CV\ </math>
This same circuit can be used in discrete time systems (such as analog to digital converters) as a track and hold circuit.  During the appropriate clock phase, the capacitor samples the analog voltage through switch one and in the second phase presents this held sampled value to an electronic circuit for processing.
 
== The Parasitic Sensitive Integrator ==
[[Image:Parasitic Sensative Inverter.png|right|400px|thumb|A Simple Switched Capacitor Parasitic-Sensitive Integrator]]
Often switched capacitor circuits are used to provide accurate voltage gain and integration by switching a sampled capacitor onto an op-amp with a capacitor <math>C_{fb}</math> in feedback.  One of the earliest of these circuits is the parasitic-Sensitive integrator developed by the Czech engineer Bedrich Hosticka.<ref>B. Hosticka, R. Brodersen, P. Gray, "MOS Sampled Data Recursive Filters.
ng Switched Capacitor Integrators," IEEE Journal of Solid State Circuits, Vol SC-12, No.6, December 1977.</ref>  Let us analyze what happens in this case. Denote by <math>T = 1 / f</math> the switching period. Recall that in capacitors
 
:<math>\text{charge} = \text{capacitance} \times \text{voltage}</math>
 
Then, at the instant when S1 opens and S2 closes, we have the following:
 
1) Because <math>C_s</math> has just charged:
 
:<math> Q_s(t) = C_s \cdot V_s(t)\, </math>
 
2) Because the feedback cap, <math>C_{fb}</math>, is suddenly charged with that much charge (by the opamp, which seeks a virtual short circuit between its inputs):
 
:<math> Q_{fb}(t) = Q_s(t-T) + Q_{fb}(t-T)\, </math>
 
Now dividing 2) by <math>C_{fb}</math>:
 
:<math> V_{fb}(t) = \frac {Q_s(t-T)}{C_{fb}} + V_{fb}(t-T)\, </math>
 
And inserting 1):
 
:<math> V_{fb}(t) = \frac {C_s}{C_{fb}} \cdot V_s(t-T) + V_{fb}(t-T)\, </math>
 
This last equation represents what is going on in <math>C_{fb}</math> - it increases (or decreases) its voltage each cycle according to the charge that is being "pumped" from <math>C_s</math> (due to the op-amp).
 
However, there is a more elegant way to formulate this fact if <math>T</math> is very short. Let us introduce <math>dt\leftarrow T</math> and <math>dV_{fb}\leftarrow V_{fb}(t)-V_{fb}(t-dt)</math> and rewrite the last equation divided by dt:
 
:<math> \frac {dV_{fb}(t)}{dt} = f \frac {C_s}{C_{fb}} \cdot V_s(t)\, </math>
 
Therefore, the op-amp output voltage takes the form:
 
:<math> V_{OUT}(t) = -V_{fb}(t) = - \frac{1}{\frac{1}{fC_s}C_{fb}} \int V_s(t)dt \, </math>
 
Note that this is an [[Operational amplifier applications#Integrator|integrator]] with an "equivalent resistance" <math>R_{eq} = \frac{1}{fC_s}</math>. This allows its ''on-line'' or ''runtime'' adjustment (if we manage to make the switches oscillate according to some signal given by e.g. a microcontroller).
 
== The Parasitic Insensitive Integrator ==
=== Use In Discrete-Time Systems ===
 
The delaying parasitic insensitive integrator has a wide use in discrete time electronic circuits such as biquad filters, anti-alias structures, and delta sigma data converters.  This circuit implements the following z-domain function:
 
:<math> H(z) = \frac{1}{z-1}</math>
 
== The Multiplying Digital to Analog Converter ==
[[Image:MDAC.png|right|frame|A 1.5 bit Multiplying Digital to Analog Converter]]
One useful characteristic of switched capacitor circuits is that they can be used to perform many circuit tasks at the same time, which is difficult with non-discrete time components. The multiplying digital to analog converter (MDAC) is an example as it can take an analog input, add a digital value to it, and multiply this by some factor based on the capacitor ratios.  The output of the MDAC is given by the following:
 
:<math> V_{Out} = \frac {V_{i} \cdot (C_{1}+C_{2}) - (d-1) \cdot V_{r} \cdot C_{2} + V_{os} \cdot (C_{1}+C_{2}+C_{p})} {C_{1} + \frac {(C_{1} + C_{2} + C_{p})} {A} } </math>
 
The MDAC is a common component in modern pipeline analog to digital converters as well as other precision analog electronics and was first created in the form above by Stephen Lewis and others at Bell Laboratories.<ref>Stephen H. Lewis et al., "A 10-bit, 20Msample/s Analog to Digital Converter, IEEE Journal of Solid State Circuits, March 1992</ref><ref>David Doan, Expert</ref>
 
== See also ==
* [[Nyquist–Shannon sampling theorem]]
* [[Aliasing]]
* [[Switched-mode power supply]]
* [[Charge pump]]
 
== References ==
{{Reflist}}
* Mingliang Liu, ''Demystifying Switched-Capacitor Circuits'', ISBN 0-7506-7907-7
 
{{DEFAULTSORT:Switched Capacitor}}
[[Category:Capacitors]]
[[Category:Electronic filter applications]]
[[Category:Electronic filter topology]]

Latest revision as of 13:54, 8 January 2015

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