en>Tassedethe: /* See also */

2013-06-09T18:51:33Z

See also

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			==Concept==
			Conceptually, pipelining puts different function units working in parallel. In computer architectures, it usually represents an implementation technique allowing multiple instructions are overlapped in execution to be parallel. Consider an informal example in the following figure. A function includes three sub-function units (F<sub>0</sub>, F1 and F2). Assume that there are three tasks (T<sub>0</sub>, T<sub>1</sub> and T<sub>2</sub>) being operated by these three function units and they can be operated independently. The time for each function unit to complete a task is the same and will occupy a slot in the schedule.
			<br>In such condition, if we put these three units and tasks in a sequential order, the required time to complete them is five slots.
			[[File:Non-pipelined.png\|center\|400px]]
			However, if we pipeline T<sub>0</sub> to T<sub>2</sub> in parallel, the aggregate time is reduced to three slots, which is smaller than in a sequential order.
			[[File:Pipelined structure function units.png\|center\|400px]]
			Therefore, it is possible for an adequate pipelined design to achieve significant enhancement on speed.

			==Costs and disadvantages==
			Pipelining does not decrease the processing time for a single task. Instead, we still need to cost the same runtime efforts on the same task when compared to a full sequential design. Please note that the advantage of pipelining is that it increases the throughput of the system when processing a stream of task.

			Nevertheless, applying too many pipelined functions usually leads to the increase of latency. The time required for a task to propagate through a full pipe prolongs. Further a pipelined system typically requires more resources and costs (buffers, circuits, processing units, memory etc.) to perform parallel working since the reuse of resources across different stages is restricted.

			==Comparison with parallel approaches==
			The other technique to enhance the efficiency of designs is called [[Parallel Processing (DSP implementation)\|parallel techniques]], which usually confuses with pipelining techniques. The core difference is that parallel techniques usually duplicate function units and distribute all the input tasks into different function units. Therefore, it can complete more tasks per unit time but suffers expensive resource costs.

			For the previous example, the parallel technique duplicate each function units into another two. Accordingly, all the tasks can be operated under duplicated function units with the same function simultaneously. The time to complete these three tasks is reduced to three slots.

			==Pipelining in FIR filters==
			Consider a 3-tap FIR filter:<ref>K.K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation, John Wiley, 1999</ref>

			<math>y(n)=ax(n)+bx(n-1)+cx(n-2)</math>

			which is as shown in the following figure.

			Assume the calculation time for multiplication units is T<sub>m</sub> and T<sub>a</sub> for add units.
			The critical path, representing the minimum time required for processing a new sample, is limited by 1 multiplication and 2 add function units. Therefore, the sample period is given by

			<math>{T_{sample} \ge T_m + 2T_a }</math>

			[[File:Pipelined FIR filters.png\|center\|350px]]

			However, such structure may not be suitable for the design with the requirement of high speed. To reduce the sampling period, we can introduce extra pipelining registers along the critical data path. Then the structure is partitioned into two stages and the data produced in the first stage will be stored in the introduced registers, delaying one clock to the second stage. The data in first three clocks is recorded in the following table.
			Under such pipelined structure, the sample period is reduced to

			<math>T_{sample} \ge T_m + T_a </math>.

			[[File:Pipelined FIR filters2.png\|center\|350px]]
			<br>
			[[File:Pipelined FIR filters table.png\|center\|550px]]

			==Pipelining in 1st-Order IIR filters==
			By combining look-ahead techniques and pipelining,<ref>Slides for VLSI Digital Signal Processing Systems: Design and Implementation John Wiley & Sons, 1999 (ISBN Number: 0-471-24186-5): http://www.ece.umn.edu/users/parhi/slides.html</ref> we are able to enhance the sample rate of target design.
			Look-ahead pipelining will add canceling poles and zeroes to the transfer function such that the coefficients of the following terms in the denominator of the transfer function are zero.
			<br><math> \{z^{-1},...,z^{-(M-1)}\} </math>

			Then, the output sample ''y''(''n'') can be computed in terms of the inputs and the output sample ''y''(''n''-''M'')
			such that there are ''M'' delay elements in the critical loop. These elements are then used to pipeline the critical loop by ''M'' stages so that the sample rate can be increased by a factor ''M''.

			<br> Consider the 1st-order IIR filter transfer function
			<br> <math>H(z)=\frac{1}{1-a*z^{-1}}</math>

			The output ''y''(''n'') can be computed in terms of the input ''u''(''n'') and the previous output.
			<br> <math>y(n) = a*y(n-1) + u(n)</math>

			In a straightforward structure to design such function, the sample rate of this recursive filter is restricted by the calculation time of one multiply-add operation.

			To pipeline such design, we observe that ''H'' has a pole at
			<br> <math>z=a, a\le1 </math>

			Therefore, in a 3-stage pipelined equivalent stable filter, the transfer function can be derived by adding poles and zeros at
			<br> <math>z=ae^{\pm(\frac{2j\pi}{3})}</math>

			and is given by
			<br><math> H(z)=\frac{1+az^{-1}+a^{2}z^{-2}}{1-a^{3}*z^{-3}}</math>

			Therefore, the corresponding sample rate can be increased by a factor 3.

			==Other Pipelined DSP systems==
			* Pipelined Walsh–Fourier transform<ref>M. R. Ashouri and [[Anthony G. Constantinides]], "A pipeline fast Walsh Fourier transform," in Proc. IEEE Int. Conf. ASSP Hartford, CT, May 9–11), pp. 515-518, 1977.</ref>
			* Pipelined unitary transforms<ref>Fino, B.J.; Algazi, V.R.; , "Parallel and pipeline computation of fast unitary transforms," Electronics Letters , vol.11, no.5, pp.93-94, March 6, 1975</ref>
			* Pipelined DFT<ref>Tzou, K.-H.; Morgan, N.P.; , "A fast pipelined DFT processor and its programming consideration," Electronic Circuits and Systems, IEE Proceedings G , vol.132, no.6, pp.273-276, December 1985</ref>
			* Pipelined FFT<ref>H. L. Gorginsky and G. A. Works, "A pipeline fast Fourier transform," IEEE Trans. Comput., vol. C-19, pp. 1015-1019, Nov. 1970.</ref>
			*etc.

			==References==
			<references/>

			[[Category:Digital signal processing]]

en>Michael Hardy: proper bolding per WP:MOS; adding a link

2012-06-24T22:22:09Z

proper bolding per WP:MOS; adding a link

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Non-wellfounded mereology - Revision history

en>Tassedethe: /* See also */

en>Michael Hardy: proper bolding per WP:MOS; adding a link