Correlation immunity - Revision history

66.90.149.68: /* Results in cryptography */

2014-10-30T02:26:43Z

Results in cryptography

← Older revision		Revision as of 04:26, 30 October 2014
Line 1:		Line 1:
	~~Hi there~~, I am ~~Sophia~~. ~~The favorite hobby for him and his children is fashion and he~~'ll be ~~beginning some thing else along with it~~. ~~Distributing production has been his profession for some time. Ohio is where~~ my ~~home~~ is but ~~my husband wants us to transfer~~.<br><br>~~Take a look at~~ my ~~webpage accurate psychic~~ readings, [http://~~help~~.~~ksu~~.~~edu.sa~~/~~node~~/~~65129 ksu~~.~~edu~~.sa],		I would like to introduce myself to you, I accurate psychic predictions [[https://www-ocl.gist.ac.kr/work/xe/?document_srl=605236 www-ocl.gist.ac.kr]] am Jayson Simcox but I don't like when individuals use my full title. She works as a journey agent but quickly she'll be on her personal. What me and my family love is bungee leaping but I've been taking on new issues lately. For years he's been residing in Mississippi and he doesn't plan on altering it.<br><br>Here is my web-site - tarot card readings, [http://myoceancounty.net/groups/apply-these-guidelines-when-gardening-and-grow/ myoceancounty.net], best psychic readings ([http://www.article-galaxy.com/profile.php?a=143251 click this site])

en>Monkbot: /* Results in cryptography */Fix CS1 deprecated date parameter errors

2014-02-04T08:50:56Z

Results in cryptography: Fix CS1 deprecated date parameter errors

← Older revision		Revision as of 10:50, 4 February 2014
Line 1:		Line 1:
	~~{{For\|the subject in [[theoretical computer science]]\|dynamic logic (modal logic)}}~~		Hi there, I am Sophia. The favorite hobby for him and his children is fashion and he'll be beginning some thing else along with it. Distributing production has been his profession for some time. Ohio is where my home is but my husband wants us to transfer.<br><br>Take a look at my webpage accurate psychic readings, [http://help.ksu.edu.sa/node/65129 ksu.edu.sa],

	In [[integrated circuit]] design, '''dynamic logic''' (or sometimes '''clocked logic''') is a design methodology in [[combinatory logic]] circuits, particularly those implemented in [[MOSFET\|MOS]] technology. It is distinguished from the so-called static logic by exploiting temporary storage of information in stray and gate capacitances.<ref name="Wanhammar1999">{{cite book\|author=Lars Wanhammar\|title=DSP integrated circuits\|url=http://books.google.com/books?id=O88sXLox7tAC&pg=PA37\|year=1999\|publisher=Academic Press\|isbn=978-0-12-734530-7\|page=37}}</ref> It was popular in the 1970s and has seen a recent resurgence in the design of high speed digital [[electronics]], particularly [[computer]] [[Central processing unit\|CPUs]]. Dynamic logic circuits are usually faster than static counterparts, and require less surface area, but are more difficult to design. Dynamic logic has a higher toggle rate than static logic<ref name="MarshallNatarajan2002">{{cite book\|author1=Andrew Marshall\|author2=Sreedhar Natarajan\|title=SOI design: analog, memory and digital techniques\|url=http://books.google.com/books?id=EgXw8sjIX0oC&pg=PA125\|year=2002\|publisher=Springer\|isbn=978-0-7923-7640-8\|page=125}}</ref> but the capacitative loads being toggled are smaller<ref name="Raj/latha">{{cite book\|author=A. Albert Raj, T. Latha\|title=VLSI Design\|url=http://books.google.com/books?id=Fg3PBibITjAC&pg=PA167\|publisher=PHI Learning Pvt. Ltd.\|isbn=978-81-203-3431-1\|page=167}}</ref> so the overall power consumption of dynamic logic may be higher or lower depending on various tradeoffs. When referring to a particular [[logic family]], the dynamic adjective usually suffices to distinguish the design methodology, e.g. ''dynamic [[CMOS]]''<ref name="JacobNg2007">{{cite book\|author1=Bruce Jacob\|author2=Spencer Ng\|author3=David Wang\|title=Memory systems: cache, DRAM, disk\|url=http://books.google.com/books?id=G-D6KFwnVsgC&pg=PA270\|year=2007\|publisher=Morgan Kaufmann\|isbn=978-0-12-379751-3\|page=270}}</ref> or ''dynamic [[Silicon on insulator\|SOI]]'' design.<ref name="MarshallNatarajan2002"/>

	Dynamic logic is distinguished from so-called ''static logic'' in that dynamic logic uses a [[clock signal]] in its implementation of [[combinational logic]] circuits. The usual use of a clock signal is to synchronize transitions in [[sequential logic]] circuits. For most implementations of combinational logic, ~~a clock signal is not even needed~~.

	The static/dynamic terminology used to refer to combinatorial circuits should not be confused with how the same adjectives are used to distinguish memory devices, e.g. [[static RAM]] from [[dynamic RAM]].<ref name="Harris2001">{{cite book\|author=David Harris\|title=Skew-tolerant circuit design\|url=http://books.google.com/books?id=fvkIoNhAnkEC&pg=PA38\|year=2001\|publisher=Morgan Kaufmann\|isbn=978-1-55860-636-4\|page=38}}</ref>

	~~== Terminology ==~~
	~~In the context of logic design, the term ''dynamic logic'' is more commonly used as compared to ''clocked logic'', as it makes clear the distinction between this type of design~~ and ~~''static logic''. To additionally confuse the matter, ''clocked logic''~~ is ~~sometimes used as a synonym for [[sequential logic]]. This usage is nonstandard~~ and ~~should be avoided.~~

	~~== Static versus dynamic logic ==~~
	The largest difference between static and dynamic logic is that in dynamic logic, a [[clock signal]] is used to evaluate [[combinational logic]]. However, to truly comprehend the importance of this distinction, the reader will need some background on static logic.

	~~In most types of logic design, termed~~ ''static logic'', there is at all times some mechanism to drive the output either high or low. In many of the popular logic styles, such as [[Transistor-transistor logic\|TTL]] and traditional [[CMOS]], this principle can be rephrased as a statement that there is always a low-impedance DC path between the output and either the supply [[voltage]] or the [[Ground (electricity)\|ground]]. As a sidenote, there is of course an exception in this definition in the case of high [[Electrical impedance\|impedance]] outputs, such as a [[tri-state buffer]]; however, even in these cases, the circuit is intended to be used within a larger system where some ~~mechanism will drive the output, and they do not qualify as distinct from static logic.~~

	In contrast, in ''dynamic logic'', there is not always a mechanism driving the output high or low. In the most common version of this concept, the output is driven high or low during distinct parts of the clock cycle. During the time intervals when the output is not being actively driven, its impedance causes it ~~to maintain a level within some tolerance range of the driven level.~~

	Dynamic logic requires a minimum [[clock rate]] fast enough that the output state of each dynamic gate is used or refreshed before the charge in the output capacitance leaks out enough to cause the digital state of the output to change, during the part of the clock cycle that the output is not being actively driven.

	~~Static logic~~ has ~~no minimum [[clock rate]]—the clock can be paused indefinitely. While it may seem that doing nothing~~ for ~~long periods of~~ time ~~is not particularly useful, it leads to two advantages:~~
	* being able to pause a system at any time makes debugging and testing much easier, enabling techniques such as [[instruction step\|single stepping]].
	* being able to run a system at extremely low [[clock rate]]s allows [[low-power electronics]] to run longer on a given battery.

	~~Being able to pause a system at any time for any duration can also be used to synchronize to asynchronous events~~. (While there are other mechanisms to do this, such as interrupts, polling loops, processor idling input pins [like RDY on the 6502], or processor bus cycle extension mechanisms such as WAIT inputs, using hardware to gate the clock to a static-core CPU is ~~simpler,~~ is ~~more temporally precise, uses no program code memory, and uses almost no power in the CPU while it is waiting. In a basic design, to start waiting, the CPU would write to a register~~ to ~~set a binary latch bit which would be ANDed or ORed with the processor clock, stopping the processor~~. A signal from a peripheral device would reset this latch, resuming CPU operation. [The hardware logic must gate the latch control inputs as necessary to ensure that a latch output transition does not cause the clock signal level to instantaneously change and cause a clock pulse, either high or low, that is shorter than normal.])

	~~In particular, although many popular CPUs use dynamic logic,~~<~~ref~~>~~[http://www.anandtech.com/show/1647/11]~~<~~/ref~~> ~~only [[static core]]s—CPUs designed with fully static technology—are usable in space satellites due to their higher [[radiation hardening\|radiation hardness]]<ref>~~
	~~[http://www.amsat-dl.org/yahue.html AMSAT-DL: "No RISC~~, ~~No Fun!"]~~
	~~by Peter Gülzow~~
	~~</ref> Most satellites do not use CMOS circuits anyway; gallium arsenide is more popular in these applications.~~

	~~Dynamic logic, when properly designed, can be over twice as fast as static logic. It uses only the~~ [[MOSFET#Single-type_MOSFET_switch\|faster N transistors]], which improve transistor sizing optimizations. Static logic is slower because it has twice the [[Capacitor\|capacitive]] [[electronic load\|loading]], higher [[Threshold voltage\|thresholds]], and uses slow P transistors for logic. Dynamic logic can be harder to work with, but it may be the only choice when increased processing speed is needed. Most electronics running at over 2 GHz these days {{When\|date=February 2011}} require the use of dynamic, although some manufacturers such as Intel have completely switched to static logic to reduce power consumption.<ref name="anandtech">http://~~www~~.~~anandtech~~.~~com/cpuchipsets/intel/showdoc~~.~~aspx?i=3448&p=9<~~/ref> Note that reducing power use not only extends the running time with limited power sources such as batteries or solar arrays (as in spacecraft), but it also reduces the thermal design requirements, reducing the size of needed heatsinks, fans, etc., which in turn reduces system weight and cost.

	~~In general, dynamic logic greatly increases the number of transistors that are switching at any given time, which increases power consumption over static CMOS.<ref name="anandtech"~~ /> There are several [[Low-power electronics\|powersaving techniques]] that can be implemented in a dynamic logic based system. In addition, each rail can convey an arbitrary number of bits, and there are no power-wasting glitches. Power-saving clock gating and asynchronous techniques are much more natural in dynamic logic.

	~~== Static logic example ==~~

	~~As an example, consider the static logic implementation of a CMOS NAND gate:~~

	~~[[File:CMOS NAND.svg\|center\|150px]]~~

	~~This circuit implements the logic function~~
	~~:<math>Out = \overline{AB}</math>~~
	~~If ''A'' and ''B'' are both high, the output will be pulled low. Whereas if either ''A'' or ''B'' are low, the output will be pulled high. At all times, the output is pulled either low or high.~~

	~~== Dynamic logic example ==~~

	~~Consider now a dynamic logic implementation of the same logic function:~~

	~~[[File:Dlnand.svg\|center\|200px]]~~

	The dynamic logic circuit requires two phases. The first phase, when ''Clock'' is low, is called the ''setup phase'' or the ''precharge phase'' and the second phase, when ''Clock'' is high, is called the ''evaluation phase''. ~~In the setup phase, the output is driven high unconditionally (no matter the values of the inputs ''A'' and ''B'')~~. ~~The [[capacitor]~~], ~~which represents the load capacitance of this gate, becomes charged. Because the transistor at the bottom is turned off, it is impossible for the output to be driven low during this phase.~~

	~~During the ''evaluation phase'', ''Clock'' is high. If ''A'' and ''B'' are also high, the output will be pulled low. Otherwise, the output stays high (due to the load capacitance).~~

	Dynamic logic has a few potential problems that static logic does not. For example, if the clock speed is too slow, the output will decay too quickly to be of use. Also, the output is only valid for part of each clock cycle, so the device connected to it must sample it synchronously during the time that it is valid.

	Also, when both ''A'' and ''B'' are high, so that the output is low, the circuit will pump one capacitor-load of charge from Vdd to ground for each clock cycle, by first charging and then discharging the capacitor in each clock cycle. This makes the circuit (with its output connected to a high impedance) less efficient than the static version (which theoretically should not allow any current to flow except through the output), and when the ''A'' and ''B'' inputs are constant and both high, the dynamic NAND gate uses power in proportion to the [[clock rate]], as long as it functions correctly. The power dissipation can be minimized by keeping the load capacitance low, but this in turn reduces the maximum cycle time, requiring a higher minimum clock frequency; the higher frequency then increases power consumption by the relation just mentioned. Therefore, it is impossible to reduce the idle power consumption (when both inputs are high) below a certain limit which derives from an equilibrium between clock speed and load capacitance.

	~~A popular implementation is [[domino logic]].~~

	~~==See also==~~

	* [[Domino logic]]
	* [[Sequential logic]]

	~~==References==~~
	~~{{Reflist}}~~
	~~'''General references'''~~
	* {{cite book\|author1=Sung-Mo Kang\|author2=Yusuf Leblebici\|title=CMOS digital integrated circuits: analysis and design\|year=2003\|publisher=McGraw-Hill\|isbn=978-0-07-246053-7\|edition=3rd}}, chapter 9, "Dynamic logic circuits" (chapter 7 in the 2nd edition)
	* {{cite book\|author=R. Jacob Baker\|title=CMOS: Circuit Design, Layout, and Simulation\|year=2010\|publisher=Wiley-IEEE\|isbn=978-0-470-88132-3\|edition=3rd}}, chapter 14, "Dynamic logic gates"
	* {{cite book\|author1=Andrew Marshall\|author2=Sreedhar Natarajan\|title=SOI design: analog, memory and digital techniques\|year=2002\|publisher=Springer\|isbn=978-0-7923-7640-8}}, chapter 7, "Dynamic SOI Design"

	~~==External links==~~
	* [http://www.cmosvlsi.com/lect9.pdf Introduction to CMOS VLSI Design – Lecture 9: Circuit Families] – David Harris' lecture notes on the subject.

	~~{{Logic Families}}~~

	~~{{DEFAULTSORT:Dynamic Logic (Digital Logic)}}~~
	~~[[Category:Logic families]]~~

en>Addbot: Bot: Migrating 1 interwiki links, now provided by Wikidata on d:q1135299

2013-03-15T07:52:26Z

Bot: Migrating 1 interwiki links, now provided by Wikidata on d:q1135299

← Older revision		Revision as of 09:52, 15 March 2013
Line 1:		Line 1:
	~~I would like~~ to ~~introduce myself~~ to ~~you~~, ~~I am Jayson Simcox but I don~~'~~t like when people~~ use ~~my complete~~ title. ~~Office supervising~~ is ~~exactly where her main income arrives from~~. ~~Her family lives~~ in ~~Ohio but her spouse desires them~~ to ~~transfer~~. As a ~~woman what she truly likes~~ is ~~style~~ and ~~she~~'~~s been~~ doing it for ~~quite~~ a ~~whilst~~.<br><br>~~my webpage~~: [http://~~c045~~.~~danah~~.~~co.kr~~/~~home~~/~~index~~.~~php~~?~~document_srl~~=~~1356970~~&~~mid~~=~~qna psychics online~~]		{{For\|the subject in [[theoretical computer science]]\|dynamic logic (modal logic)}}

			In [[integrated circuit]] design, '''dynamic logic''' (or sometimes '''clocked logic''') is a design methodology in [[combinatory logic]] circuits, particularly those implemented in [[MOSFET\|MOS]] technology. It is distinguished from the so-called static logic by exploiting temporary storage of information in stray and gate capacitances.<ref name="Wanhammar1999">{{cite book\|author=Lars Wanhammar\|title=DSP integrated circuits\|url=http://books.google.com/books?id=O88sXLox7tAC&pg=PA37\|year=1999\|publisher=Academic Press\|isbn=978-0-12-734530-7\|page=37}}</ref> It was popular in the 1970s and has seen a recent resurgence in the design of high speed digital [[electronics]], particularly [[computer]] [[Central processing unit\|CPUs]]. Dynamic logic circuits are usually faster than static counterparts, and require less surface area, but are more difficult to design. Dynamic logic has a higher toggle rate than static logic<ref name="MarshallNatarajan2002">{{cite book\|author1=Andrew Marshall\|author2=Sreedhar Natarajan\|title=SOI design: analog, memory and digital techniques\|url=http://books.google.com/books?id=EgXw8sjIX0oC&pg=PA125\|year=2002\|publisher=Springer\|isbn=978-0-7923-7640-8\|page=125}}</ref> but the capacitative loads being toggled are smaller<ref name="Raj/latha">{{cite book\|author=A. Albert Raj, T. Latha\|title=VLSI Design\|url=http://books.google.com/books?id=Fg3PBibITjAC&pg=PA167\|publisher=PHI Learning Pvt. Ltd.\|isbn=978-81-203-3431-1\|page=167}}</ref> so the overall power consumption of dynamic logic may be higher or lower depending on various tradeoffs. When referring to a particular [[logic family]], the dynamic adjective usually suffices to distinguish the design methodology, e.g. ''dynamic [[CMOS]]''<ref name="JacobNg2007">{{cite book\|author1=Bruce Jacob\|author2=Spencer Ng\|author3=David Wang\|title=Memory systems: cache, DRAM, disk\|url=http://books.google.com/books?id=G-D6KFwnVsgC&pg=PA270\|year=2007\|publisher=Morgan Kaufmann\|isbn=978-0-12-379751-3\|page=270}}</ref> or ''dynamic [[Silicon on insulator\|SOI]]'' design.<ref name="MarshallNatarajan2002"/>

			Dynamic logic is distinguished from so-called ''static logic'' in that dynamic logic uses a [[clock signal]] in its implementation of [[combinational logic]] circuits. The usual use of a clock signal is to synchronize transitions in [[sequential logic]] circuits. For most implementations of combinational logic, a clock signal is not even needed.

			The static/dynamic terminology used to refer to combinatorial circuits should not be confused with how the same adjectives are used to distinguish memory devices, e.g. [[static RAM]] from [[dynamic RAM]].<ref name="Harris2001">{{cite book\|author=David Harris\|title=Skew-tolerant circuit design\|url=http://books.google.com/books?id=fvkIoNhAnkEC&pg=PA38\|year=2001\|publisher=Morgan Kaufmann\|isbn=978-1-55860-636-4\|page=38}}</ref>

			== Terminology ==
			In the context of logic design, the term ''dynamic logic'' is more commonly used as compared to ''clocked logic'', as it makes clear the distinction between this type of design and ''static logic''. To additionally confuse the matter, ''clocked logic'' is sometimes used as a synonym for [[sequential logic]]. This usage is nonstandard and should be avoided.

			== Static versus dynamic logic ==
			The largest difference between static and dynamic logic is that in dynamic logic, a [[clock signal]] is used to evaluate [[combinational logic]]. However, to truly comprehend the importance of this distinction, the reader will need some background on static logic.

			In most types of logic design, termed ''static logic'', there is at all times some mechanism to drive the output either high or low. In many of the popular logic styles, such as [[Transistor-transistor logic\|TTL]] and traditional [[CMOS]], this principle can be rephrased as a statement that there is always a low-impedance DC path between the output and either the supply [[voltage]] or the [[Ground (electricity)\|ground]]. As a sidenote, there is of course an exception in this definition in the case of high [[Electrical impedance\|impedance]] outputs, such as a [[tri-state buffer]]; however, even in these cases, the circuit is intended to be used within a larger system where some mechanism will drive the output, and they do not qualify as distinct from static logic.

			In contrast, in ''dynamic logic'', there is not always a mechanism driving the output high or low. In the most common version of this concept, the output is driven high or low during distinct parts of the clock cycle. During the time intervals when the output is not being actively driven, its impedance causes it to maintain a level within some tolerance range of the driven level.

			Dynamic logic requires a minimum [[clock rate]] fast enough that the output state of each dynamic gate is used or refreshed before the charge in the output capacitance leaks out enough to cause the digital state of the output to change, during the part of the clock cycle that the output is not being actively driven.

			Static logic has no minimum [[clock rate]]—the clock can be paused indefinitely. While it may seem that doing nothing for long periods of time is not particularly useful, it leads to two advantages:
			* being able to pause a system at any time makes debugging and testing much easier, enabling techniques such as [[instruction step\|single stepping]].
			* being able to run a system at extremely low [[clock rate]]s allows [[low-power electronics]] to run longer on a given battery.

			Being able to pause a system at any time for any duration can also be used to synchronize to asynchronous events. (While there are other mechanisms to do this, such as interrupts, polling loops, processor idling input pins [like RDY on the 6502], or processor bus cycle extension mechanisms such as WAIT inputs, using hardware to gate the clock to a static-core CPU is simpler, is more temporally precise, uses no program code memory, and uses almost no power in the CPU while it is waiting. In a basic design, to start waiting, the CPU would write to a register to set a binary latch bit which would be ANDed or ORed with the processor clock, stopping the processor. A signal from a peripheral device would reset this latch, resuming CPU operation. [The hardware logic must gate the latch control inputs as necessary to ensure that a latch output transition does not cause the clock signal level to instantaneously change and cause a clock pulse, either high or low, that is shorter than normal.])

			In particular, although many popular CPUs use dynamic logic,<ref>[http://www.anandtech.com/show/1647/11]</ref> only [[static core]]s—CPUs designed with fully static technology—are usable in space satellites due to their higher [[radiation hardening\|radiation hardness]]<ref>
			[http://www.amsat-dl.org/yahue.html AMSAT-DL: "No RISC, No Fun!"]
			by Peter Gülzow
			</ref> Most satellites do not use CMOS circuits anyway; gallium arsenide is more popular in these applications.

			Dynamic logic, when properly designed, can be over twice as fast as static logic. It uses only the [[MOSFET#Single-type_MOSFET_switch\|faster N transistors]], which improve transistor sizing optimizations. Static logic is slower because it has twice the [[Capacitor\|capacitive]] [[electronic load\|loading]], higher [[Threshold voltage\|thresholds]], and uses slow P transistors for logic. Dynamic logic can be harder to work with, but it may be the only choice when increased processing speed is needed. Most electronics running at over 2 GHz these days {{When\|date=February 2011}} require the use of dynamic, although some manufacturers such as Intel have completely switched to static logic to reduce power consumption.<ref name="anandtech">http://www.anandtech.com/cpuchipsets/intel/showdoc.aspx?i=3448&p=9</ref> Note that reducing power use not only extends the running time with limited power sources such as batteries or solar arrays (as in spacecraft), but it also reduces the thermal design requirements, reducing the size of needed heatsinks, fans, etc., which in turn reduces system weight and cost.

			In general, dynamic logic greatly increases the number of transistors that are switching at any given time, which increases power consumption over static CMOS.<ref name="anandtech" /> There are several [[Low-power electronics\|powersaving techniques]] that can be implemented in a dynamic logic based system. In addition, each rail can convey an arbitrary number of bits, and there are no power-wasting glitches. Power-saving clock gating and asynchronous techniques are much more natural in dynamic logic.

			== Static logic example ==

			As an example, consider the static logic implementation of a CMOS NAND gate:

			[[File:CMOS NAND.svg\|center\|150px]]

			This circuit implements the logic function
			:<math>Out = \overline{AB}</math>
			If ''A'' and ''B'' are both high, the output will be pulled low. Whereas if either ''A'' or ''B'' are low, the output will be pulled high. At all times, the output is pulled either low or high.

			== Dynamic logic example ==

			Consider now a dynamic logic implementation of the same logic function:

			[[File:Dlnand.svg\|center\|200px]]

			The dynamic logic circuit requires two phases. The first phase, when ''Clock'' is low, is called the ''setup phase'' or the ''precharge phase'' and the second phase, when ''Clock'' is high, is called the ''evaluation phase''. In the setup phase, the output is driven high unconditionally (no matter the values of the inputs ''A'' and ''B''). The [[capacitor]], which represents the load capacitance of this gate, becomes charged. Because the transistor at the bottom is turned off, it is impossible for the output to be driven low during this phase.

			During the ''evaluation phase'', ''Clock'' is high. If ''A'' and ''B'' are also high, the output will be pulled low. Otherwise, the output stays high (due to the load capacitance).

			Dynamic logic has a few potential problems that static logic does not. For example, if the clock speed is too slow, the output will decay too quickly to be of use. Also, the output is only valid for part of each clock cycle, so the device connected to it must sample it synchronously during the time that it is valid.

			Also, when both ''A'' and ''B'' are high, so that the output is low, the circuit will pump one capacitor-load of charge from Vdd to ground for each clock cycle, by first charging and then discharging the capacitor in each clock cycle. This makes the circuit (with its output connected to a high impedance) less efficient than the static version (which theoretically should not allow any current to flow except through the output), and when the ''A'' and ''B'' inputs are constant and both high, the dynamic NAND gate uses power in proportion to the [[clock rate]], as long as it functions correctly. The power dissipation can be minimized by keeping the load capacitance low, but this in turn reduces the maximum cycle time, requiring a higher minimum clock frequency; the higher frequency then increases power consumption by the relation just mentioned. Therefore, it is impossible to reduce the idle power consumption (when both inputs are high) below a certain limit which derives from an equilibrium between clock speed and load capacitance.

			A popular implementation is [[domino logic]].

			==See also==

			* [[Domino logic]]
			* [[Sequential logic]]

			==References==
			{{Reflist}}
			'''General references'''
			* {{cite book\|author1=Sung-Mo Kang\|author2=Yusuf Leblebici\|title=CMOS digital integrated circuits: analysis and design\|year=2003\|publisher=McGraw-Hill\|isbn=978-0-07-246053-7\|edition=3rd}}, chapter 9, "Dynamic logic circuits" (chapter 7 in the 2nd edition)
			* {{cite book\|author=R. Jacob Baker\|title=CMOS: Circuit Design, Layout, and Simulation\|year=2010\|publisher=Wiley-IEEE\|isbn=978-0-470-88132-3\|edition=3rd}}, chapter 14, "Dynamic logic gates"
			* {{cite book\|author1=Andrew Marshall\|author2=Sreedhar Natarajan\|title=SOI design: analog, memory and digital techniques\|year=2002\|publisher=Springer\|isbn=978-0-7923-7640-8}}, chapter 7, "Dynamic SOI Design"

			==External links==
			* [http://www.cmosvlsi.com/lect9.pdf Introduction to CMOS VLSI Design – Lecture 9: Circuit Families] – David Harris' lecture notes on the subject.

			{{Logic Families}}

			{{DEFAULTSORT:Dynamic Logic (Digital Logic)}}
			[[Category:Logic families]]

en>Yobot: /* References */WP:CHECKWIKI error fixes + general fixes using AWB (8024)

2012-03-19T16:15:53Z

References: WP:CHECKWIKI error fixes + general fixes using AWB (8024)

New page

I would like to introduce myself to you, I am Jayson Simcox but I don't like when people use my complete title. Office supervising is exactly where her main income arrives from. Her family lives in Ohio but her spouse desires them to transfer. As a woman what she truly likes is style and she's been doing it for quite a whilst.<br><br>my webpage: [http://c045.danah.co.kr/home/index.php?document_srl=1356970&mid=qna psychics online]